Invalid values obtained sporadic FlexRIO card

Hello

I can't acquire the data of my FlexRIO (SMU-7962R + OR-5734). I write custom code instead of using FIDL building blocks, because the FIDL requires a design of master-slave to trigger synchronized, while I need each FlexRIO card to activate it.

In short, this is a small test case (I tried with a 40 MHz clock and a clock of 10 MHz, with the same results):

FPGA

Host

While most of the output looks ok (i.e. the look of signals as input signals), I have several bursts of corrupt samples. I often get spikes that equals the I16 max/min value, although there are cases of non-max tips too.

Interesting fact:

  • Each FlexRIO card seems to have exactly 1 channel of misconduct.

  • The channel varies from cards (for example RIO1 gets spikes in AI0, while RIO2 gets spikes to AI3)

  • When I repeatedly trigger acquisition on the same card, I see a very similar form 'noise' every time. Different cards produce different forms "noise".

  • I see spikes when I use the FIDL pre-built instead of my own code examples (maybe I need to make some sort of synchronization?)

Screenshots below.

  • Orange graphics are supposed to be zeros.

  • The green graph is supposed to show a pure sinusoidal signal.

What could be the problem and how can I solve this problem?

Thank you!

Zoomed in

You must acquire the 5734 data in the area of the sample clock. Reading from the node HAVE in any other field clock causes the glitching you see.

Tags: NI Hardware

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