Is an FPGA host Interface a shared resource lock?

I'm curious to know if the FPGA host Interface node is a shared resource. Which means, if I have a loop timed on a target time real LabVIEW (e.g. cRIO) who is reading and writing of the FPGA using the Interface of the host. The determinism of this loop will be concerns touched if I have other signls on the FPGA using the Interface of the host in a separate loop (a loop delay or a normal life while loop).

More tersely said, is the Interface to the FPGA host a shared resource that can cause a reversal of priority if called from two separate loops?

Thank you.

Hey Southern_Cross,

The Interface of the host as a whole is not a shared resource that is protected by a global lock, but calls to functions of specific host interface can acquire locks to protect shared resources. If you let me know what you call of each loop, I can let you know what kind of interactions are possible.

Priority inversion should not happen. You see something akin to the inversion of priority for you? If so, I would be interested in the details, because this is the kind of issue, we take seriously.

Thank you

Sebastian

Tags: NI Software

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