LV FPGA delay seen between subsequent of the SCTL

Hi all

I'm developing a customized with a FAM 6581 LV FPGA and a FlexRIO SPI. I need to communicate with the microcontroller requires that I write 16-bit data on a clock edge followed 8 clock cycles for data through the process in the Aluminum and the clock microphone on the rise. Then I need to provide others 16 clocks to clock on the 16-bit result. I did initially with 3 single-Cycle timed loops, one for each section. Am I on the references of the IO of each SCTL following SCTL to get the correct data stream. When I look at signals with a Logic Analyzer I see each section works correctly, but there is an approximate time 504ns between each section of the code. I was expecting sort, perhaps only a single clock cycle delay between s SCTL but not much. Anyone got any ideas on what could be the cause and how can I fix this?

Thank you all,

Nick

Instead of using several distinct SCTLs, consider using a SCTL as a state machine that can handle these three steps.

Tags: NI Software

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