NEITHER 9870

I try to use NI 9870 with a loop timed in FPGA programming.  I have the output defined in the FPGA program and the host program that I'm reading the given recived.  However, my host is a loop timed with 3ms loop timer.  I read recently that NI 9870 can't Timed single Cycle (SCTLs) loop in the FPGA.  Is this true? is there a way to get around this?

Kamal

A SCTL on fpga requires the code to run in a single cycle, so at 40 Mhz, it comes to 25nS.  not a lot of modules support this mainly due to transfer of data to the module.  Your 8970 can easily stand 3mS loop rates, simply use a while loop and loop timer.  what I don't understand is that say you that the host has a timed loop 3ms.  How do you transfer data to the FPGA?  I suggest maybe a DMA, then the FPGA knows nothing of the synchronization, it sends data just when she has something in the dma (-1 timeout on FPGA dma read, no timer necessary loop) on the 9870 think time-out settings in the properties of the module, and use a node to call to check the errors CAN without these the node of your writing could easily hang indefinitely if there are errors on the CAN bus.  In the Finder of the example, there is a good example of sending data by querying the controls FPGA which is also a good method.

I hope this helps.

Michael.

Tags: NI Hardware

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