Not sure I understand the FPGA FIFO resources

Hi all

I'm having a problem with FPGA FIFOs.  I'm performing a target-to-Host DMA transfer, and I have two different configurations that use the same FIFO, but have radically different resource allocation.  In the first case below, FIFO is a loop which will be called 1 time k each time the loop runs.  In this case, when you map the Slice LUTs used are about 15%

In the second case, below, the FIFO is called once when the while loop is executed.  In this case, the use of estimated resources regarding the Slice LUTs is 107%. I guess I don't know why this behavior should be expected.  Can someone explain this to me?  Thanks, Matt

Yet once again, take a look at the link resource use statistics. You do most or all mathematics in 64-bit and use of resources grows with the increase of the bit widths. In particular, logical shift, you use a lot, is a particularly costly and to a 64-bit value requires choice tables more than two times more than the same operation on a 32-bit value. I suspect that the implementation is really a huge table - for every possible way of entry that there is a corresponding output. This allows him to be very fast at the expense of the FPGA fabric. Other mathematical operations (add, subtract, multiply) are more space-efficient.

The entire block of logic in the lower left corner of your VI is a candidate easy to encapsulate in a single cycle timed loop, which can save you space, even if it will save especially flip flops and not lookup tables.

Tags: NI Software

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