Optimisation of the FPGA pls help

Hello, I am a new player in the programming of FPGA and LV. I've set up a project, but using FPGA is more than 150 percent too high. I've read a lot about optimization, but I think that I always do anything much wrong. Please check my code and tell me where the dog is buried. I joined only a few VI.

Please download the project as a zipfile, directly to this forum.  I, at least, will not download files from unknown foreign sites.

charlie87 wrote:

at nathand : I do not understand the idea of making SCTL acting as the loop. Do you have some examples?

I thought that Hight Throuthput math is better then standard digital mathematics. If this isn't the case, please explain.

I need feedback node to store the previous value to the derivation and integration where I now the difference. I know no better way how to do it. Do you have?

Comment nodes are fine for this purpose, I was just trying to understand if there was a mathematical need for them or if you were trying to use them for some sort of pipelining.

The math broadband are not necessarily better than the standard numerical calculation.  Please see Help for "the use of Math functions broadband.  This document: "National Instruments recommends to use the LabVIEW digital unless you need the benefits that offer the features high-speed mathematical."

Here's how you can implement a loop as a single cycle timed loop.  Will not compile on my machine, although - you need to solve problems with excessively across the point values fixed first, as dan_u noted.

Tags: NI Software

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