Similar Questions

• Question about 6674 t FlexRIO 7966R and Module AT - 1120 FAM DSTARA

  Hello

  I have a chassis SMU-1085 and following committees installed:

  Slot 10: Module of synchronization for the SMU-6674 t

  Slot 02: SMU-7966R FPGA

  Attached to the SMU-7966R FPGA is a module of adaptation AT1120.

  I'm trying to provide a clock of 125 MHz by the 6674 t the bottom of basket DDS output to power the clock DSTARA the SMU-7966R and then the module adaptation AT1120 as the clock of the DAC.

  I'm currently using a modified version of the AT-1120 Getting Started project (https://decibel.ni.com/content/docs/DOC-26331) and have the Adapter Module set to take an internal clock and from FPGA clock as specified in the AT-1120 user manual:
  
  
  
  For my adapter module CLIP on the FPGA VI I have the clockin set to the DStarA Clock as shown below:
  
  
  
  For my FlexRIO 7966R I have the toplevel clock set to the defautl 40 MHz onboard clock. I cannot use an external clock for this:
  
  
  
  Then I have my SCTL clock set to the DStarA Clock:
  
  
  
  For simplicty sake, I am trying to feed the DSTARA clock using the test panel in NI Max with 6674T as follows. Becuase my FPGA is in slot 2 on the 1085 Chassis, I am feeding the 125 MHz DDS frequency to PXIe_DStarA6 based on the PXIe-1085 user manuel (http://www.ni.com/pdf/manuals/373712e.pdf) specified timing DStar lines:
  
  
  
   
  
  However, when I try and run my VI with all of these settings I get the following error:
  
  
  
   
  
  Has anyone seen this, or can anyone advise regarding this? Maybe I'm using the DStarA lines wrong or something, but I'm not sure. Any help or suggestions from the community would be great! 
  
   
  
  Thanks for all your help!
  
   
  
  -GMac
  
   
  
   
  

  GMac,

  Hello!

  There are three things that I think that in the combination will solve this problem.

  1.) can not included it in your screenshots, but there is an extra step you need to do to use the DSTAR. The bitfile you are using must be respected with a parameter that indicates the FlexRIO use the signal DSTARA.

  1. Right click on the Module adaptation of your project and select Properties
  2. Go to the category details
  3. Make sure that "PXIe_DStarA" is selected in the section "IoModSyncClock".
  4. If it is checked, then you have probably already chosen it and compiled your bitfile. If it is not selected, or you are not sure if you have compiled the adjustment, re - compile your Bitfile.

  2.) also, what you see was a known problem that has been fixed in Active Techonologies (AT) last software update (version 1.8). While I'm not 100% certain, I don't think the example started to get has been updated so that it includes all the screws of the ATs software update. Similarly, the bitfiles provided with this sample would have not generated with the CLIP included in the latest version of the software.

  I suggest the following:

  1. Download the latest version of the software (version 1.8) AT their site
  2. Use the example that comes with their software to confirm that you can clock at DSTARA
  3. Update of our example started to use the latest version of the software. (generate new bitfies, replace the old screw in the directory of the project with new screws)
  4. Confirm your new works for example.

  3.) generate a signal from 125 MHz of the 6674 t, not 124,98 MHz. The material is expected a 125 MHz signal. Dialog said 124,98 MHz with workaround for an odd present which was causing compilation failures.  If you would like more information about this, let me know and I'll fill it in you read this post on the forum: http://forums.ni.com/t5/LabVIEW/7966R-DSTARA-Clock-and-AT-1120/m-p/2932916#M847692

  I hope this helps!

• Component-level IP: generate and check the syntax error

  I tried to create a component for my device myRio level IP. I encountered this problem:

  File level information extraction superior synthesis. Please wait...
  
  Processing files...
  
  Vivado Simulator 2014.4
  
  Copyright 1986-1999, 2001-2014 Xilinx, Inc. All rights reserved.
  
  Running: C:/NIFPGA/programs/Vivado2014_4/patches/AR62969/vivado/bin/unwrapped/win32.o/xelab.exe xil_defaultlib.conf3B887A0FF22442ACAD7559670A4D090A-L xil_defaultlib-L unisim-L unimacro-L xilinxcorelib-L secureip-snapshot dll high - prj - clipsyn.prj
  
  Multi-threading is on. Using 6 son of a slave.
  
  Determine the order of compilation of HDL files.
  
  INFO: VHDL file analysis of [VRFC 10-163] 'C:/NIFPGA/iptemp/clip6BEF358BFCFF45AD8C68F5AB63F88A19/top.vhd' in the xil_defaultlib library
  
  INFO: [VRFC 10-307] analysis top part entity
  
  INFO: VHDL file analysis of [VRFC 10-163] 'C:/NIFPGA/iptemp/clip6BEF358BFCFF45AD8C68F5AB63F88A19/clock_div.vhd' in the xil_defaultlib library
  
  INFO: [VRFC 10-307] analysis feature clock_div
  
  INFO: VHDL file analysis of [VRFC 10-163] 'C:/NIFPGA/iptemp/clip6BEF358BFCFF45AD8C68F5AB63F88A19/pwmbuffer.vhd' in the xil_defaultlib library
  
  INFO: [VRFC 10-307] analysis feature pwmBuffer
  
  From static development
  
  Completed the static development
  
  Starting analysis of simulation data flow
  
  Filled with simulation data flow analysis
  
  Resolution for the simulation time is 1ps
  
  Compile the std.standard package
  
  Compile the ieee.std_logic_1164 package
  
  Compile the package ieee.numeric_std
  
  Compilation of behavioural architecture of the entity xil_defaultlib.clock_div [\clock_div (40000000,400000)------]
  
  Compilation of behavioural architecture of the entity xil_defaultlib.pwmBuffer [pwmbuffer_default]
  
  Compilation of behavioural architecture of the entity xil_defaultlib.top [top]
  
  GCC.exe: internal error: abandoned (collect2 program)
  
  Please submit a bug report.
  
  to get instructions.
  
  Correct the above error and check the syntax again.

  I have labview 2015 and vivado 2014.4 running on windows 8.1. Thank you in advance.

  Thank you for your response.

  I solved the problem. It is apparently caused by minGW installed with 14.4 vivado which does not work with windows 8. So, I replaced the minGW on vivado record 14.4 with the latest version of minGW.

• Example of project 5791 NI and NI-SMU-7972R

  Hello

  Is there an example project in 2015 of LabView for data dissemination using 5791 NI FlexRIO and SMU-7972R Simple?

  We checked that the sample project in LabView 2015 contains only example with the following combinations:

  - NEITHER 5791 with SMU-7966R, and

  - NEITHER 5791 with SMU-7975R

  Any answer will appreciated.

  Thank you.

  If you add a 7972 to the project you can simply highlight all the files, the VI and the clock of 200 MHz under the 7975 and copy them into the 7972. From there all you ned to do is add the i/o Module to the target and're you good to go.

  

• Amplitude varying on the change of the input frequency

  Hello

  I using NOR-5752 scanner to measure the analog inputs of high frequency. NOR-5752 is connected to the module FLEX RIO 7966R and entry to the NOR-5752 is provided using the SMB-2145 terminal outlet box.

  Now, I'm the animals the 0.5Vpp @ different frequencies of tektronix generator of functions directly and by measuring using the digitizer. On the change of the frequency, measured amplitude is changed.

  All,

  For the NI 5752 frequency response strange behavior is expected.  CDA in NI 5752 is the TI AFE5801 (http://www.ti.com/lit/ds/slos591d/slos591d.pdf), and if you look at Figure 19 (p.13), you will see that frequency response of the ADC is only flat after about 1 Mhz.  I checked this with our R & D Department and they said they are not aware of any combination of parameters that gives a uniform frequency response at these low frequencies.

  If a flat frequency response is necessary for these lower frequency ranges, then the 5751 NOR is much better suited because it has a different ADC.  (http://www.ni.com/pdf/manuals/375602b.pdf)  The frequency response of this device is very flat in the low frequencies (see Figure 11 p.15).

  So both devices, NI 5752 and the 5751 OR are designed to measure different frequency ranges.  I hope this helps.

• Peer to peer between SMU-5451 and SMU-7966R

  Hello

  I would like to connect two devices - SMU-5451(waveform generator) and SMU-7966R(NI FlexRIO) with the P2P streaming. I want to transmit data from FPGA to the generator and I took the example of NOR-FGEN. When I started host-vi, there is an error (see photo).

  

  

  What I am doing wrong?

  Try to set the Active Channel property before the active P2P. Property nodes run from top to bottom, so the Active Channel property must be set before calling the property Enabled of the P2P.

• FPGA: update w / 14,4, fails w / Vivado 2013.4

  My FPGA code that compiled fine in LV 2011, then 2013 LV (using Xilinx 14.4). I didn't contact for some time...

  The upgrade to SP1 2014 LV, I believe that I have to re - compile to get the bit file to run on the target of the cRIO. However, now it does not compile. Cloud compiler error of timing. Clouds (local and compiler and elsewhere) report using Vivado 2013.4

  The code handles a moudle of analog input of series C 9205. 6 of the 32 channels are run by a calculation of RMS. A time loop is set to do this each 185 uSec (9205 card channels = minimum update 4uSec * 32 channels = 128uS = maximum theoretical to run the FPGA and to obtain valid data). Each value of 650 samples a new RMS is calculated.

  The rest of the channels get on average, 8 samples are averaged every 100th iteration of the loop above.

  The timing of the loop is a front panel control. I tried this increasing by 185 to 200 uSec, but it does not help. All inputs and outputs to the FPGA VI are written in / reading of the *(cRIO-9068) of host real time be using the controls on the front panel.

  This code has not changed in a very long time. I could share it if it helps.

  My questions around the investigate Center window timing results. Here, nothing seems useful. What is "path 1' and how is it related to the block diagram? View items and path are inhibited. I have tried to change the build - optimize the performance and optimize for area etc... but the compilation always fails.

  I will create a ticket with NEITHER. But thought pehaps someone here might have additional guidance.

  

  For applications using hybrid...

  (1) update install to 14.5 CompactRIO: C Series Module Support 14.6

  (2) change of generation to optimize performance

• Choose ISE or Vivado Xilinx tools for a specific compilation of FPGA

  Hello

  Is there a way to specify what version of Xilinx Compilation tools to use when compiling an FPGA VI? I want to try the version Vivado tools rather than the version of ISE to see if there is an improvement. I have listed some information on my setup below.

  It's my current setup:
  NI5772 / PXIe7966 digitizer and FPGA
  SMU-1082 chassis
  SMU-PCIe8388 / SMU-PCIe8389 controller
  LabVIEW 2014

  In the past, I used the LabVIEW 2014 FPGA Xilinx tools 14.7 Module to compile my code. But I also want to try the version of Vivado, "LabVIEW FPGA Module Xilinx tools Vivado 2013.4 2014', to see if it gives better results."

  Page-based "compatibility between tools Compilation of Xilinx and FPGA hardware OR" here:
  http://www.NI.com/product-documentation/53056/en/
  Looks like the PXIe7966 FPGA must be compatible with the tools of Vivado 2013.4.

  I tried to uninstall the version 14.7 ISE tools, and install the 2013.4 of tools Vivado (so Vivado 2013.4 tools are the only xilinx tools installed on the computer). But LabVIEW complains that the ISE 14.7 tools are not installed and does not compile the FPGA VI.

  Thank you!
  Michael

  This FPGA is a Virtex-5 FPGA, so you're stuck with ISE.  You need a card FPGA that either uses the architecting chip (I think it was only in cRIOs) or 7 Kintex to use the compiler to Vivado.

• «TclStackFree: invalid freePtr.» Call out of sequence? "- Vivado 2014.4 Windows 10 error near PumaK7Top Synth 8-3917

  I use the tools of Compilation NI LabVIEW 2015 SP1 FPGA Xilinx for Vivado 2014.4 on Windows 10. The LabVIEW project that contains the files that I want to compile is attached. The code consists of two periods loops, one for the collection of data from a detector and one for the processing of these data. Treatment of information in loop... complicated. I crushed 11 filters the data in parallel. To make this easier for me, I put them in a loop for. Each filter has a 23 - a state machine which deals out of 4 filters box. I'm also using a huge array that contains all the data points 500 + last rather than using 44 FIFOs. It is, once again, to make my life easier.

  In the LabVIEW code, the data processing loop is a timed loop which contains a large table and a loop for (the loop is a LabVIEW shenanigan that allows me to run 11 filters in parallel). The loop contains a structure case 23 cases. To get this code compiles successfully, I got rid of my machine States and left behind a structure of cases case 1. It is of no use to me, but it's the closest thing to my code that compiles successfully. When I shot this in a case 2-State structure, he didn't, even when I have nothing in the second case and left all the outputs to their default values. I would fix the VHDL files, the build tools to produce from this code, but LabVIEW crypt, so I don't think they will help you a lot.

  When the compiler fails, it almost always seizes 12 GB of memory (I have 64GB available, so this isn't the problem), is sitting on it for a while, and then begins to write to disk quickly while decreasing memory load before giving me the error message. Not sure if this is useful at all, but it's something that happens to each failure that does not occur when I succeed.

  I looked this error and there are two common refrains: use options to run optimized rather than the default options and make sure that your computer uses only Latin characters in the name of your computer. I already use only Latin characters in my name of the computer, and I also tried to use the options of execution-Optimzed.

  In my view, it is a LabVIEW error, not a mistake of Xilinx, because it is close to PumaK7Top, which is a virtual hard disk file LabVIEW owner.

  Yes, now, it seems it might be a memory problem. See the attachment below for instructions on FPGA code optimization:

  Optimization of screw FPGAS for speed and size (FPGA Module)

  https://zone.NI.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/optimizing_fpga_vis/

• OR 7966R - the bitfile deployment problem.

  I've implemented the following

  SMU 1085 three chasiss NOR SMU 7966R FPGA inside.

  I'm connected to a remote host via MXI using an SMU-8381

  I tried to run the NI 5761 - single CLIP.lvproj sample provided with race and LabVIEW examples just to get things to the top.

  and I get the following message if poster on all targets...

  Compilation went well but can't deploy the bitfile...

  Kind regards

  Maciej

  To the hour... so my bad, I forgot to mention one thing in my game to the top.

  I got a sync 6674 t module that is currently seems to be a little tired. Since I don't have the intention to use it then.

  I removed the chassis and things started work very well.

  It seems that it has caused problems.

  Kind regards

  Maciej

• I have an ipod touch 128 GB... but I'm almost to reach its maximum.  I want to do is buy a new ipod touch 128 GB and add new music without synchronizing the entire library to it... I have 2 ipods in conjunction with other copies

  I have an ipod touch 128 GB... but I'm almost to reach its maximum.

  I want to do is buy a new ipod touch 128 GB and add new music without synchronizing the entire library to it... I have 2 ipods in conjunction with the other copies of the other.

  is this possible?

  What should I do?

  Matt

  When you get the new iPod, you can use iTunes on your computer to select and synchronize the music you want on it, in the same way that you synchronize your current iPod - your iTunes will recognize them as different devices and will remember your choice of synchronization for each, it will not (unless, for example, you restore the backup of your current on her iPod) put the same content on both.

  (I asked for your post be moved to the iPod Touch forum, where you have posted is the iPad forum use.)

• Why my notes sync between my Mac and iPhone?

  I have my MacBook Pro with Mac OS X 10.9.5 Mavericks and my iPhone is running iOS 10.0.1 and used to synchronize my notes! Is it because of the huge gap in operating systems? I SHOULD update my Mac to Mac OS 10.10 + for this problem? Thank you!

  In order to synchronize Notes between your Mac and iPhone, you must configure iCloud > http://www.apple.com/icloud/setup/

  But this requires macOS Sierra 10.12, the latest available version and the last iOS available for your iPhone.

• Photos, iCloud and OneDrive sync

  Hi all

  I have a question on how to better organize my photo library.

  For the moment, on my space OneDrive (mapped to a partition on my MacBook SSD), I have a folder called 'Images' containing just about all of my photos and organized by folders.

  Since my tech ecosystem is roughly marked Apple (iPhone, iPad and MacBook), I would use the power and versatility of the Photos and iCloud, so that everything remains in all of my devices and free space memory iPhone sync.

  Here's the question: I want to keep my pictures saved on OneDrive, then put the Photos on my Mac to view photos from this folder and use iCloud to share through my devices.

  -I see the same folder structure on iPhone and iPad a synchronization is complete?

  -More important, if I take a picture with my iPad, it will be placed not only on iCloud but also automatically added pictures on Mac which, in turn, puts it in the folder of photos on my OneDrive?

  -Finally, take pictures of my iDevices will store them in the film. If I move them into folders, photos will be mapped (copied to iCloud) on my other devices constantly (in the folder)?

  I would like to notice I'm not trying to avoid using iCloud premium space - I already have a subscription plan of 50 GB that I don't mind mounted. I just keep having just all my photos on OneDrive.

  Thank you in advance for any comments you may have!

  Paul

  The answer is simply not

  The photo library can not be stored on a basic system to pictures not work will have a referenced library, so you may not have a local library references photos on a disc - the photo library can be on a local drive connected directly to the Mac OS Extended format

  You can synchronize between the Mac and IOS devices using iCloud library that synchronizes the photos and the structure of the album/folder between devices

  When you import pictures you can export them to your OneDrive record and have a copy (not associate Photos somehow) on a disk

  You can not have the same physical pictures in Photos and on one disc - each must have its own copy of the Photo

  http://www.Apple.com/icloud/photos/

  LN

• Video and photos of backup

  Hello

  Anyone know the best way to back up photos and videos I took Iphone 6 my mom.

  I just got a new Iphone 6 more and have an icloud account, she has one more.  I don't know how to proceed.

  Thank you

  This article can help you:

  The backup of your iPhone, iPad and iPod touch - Apple Support

  You get free 5 GB of storage iCloud. If you want to save more than 5 GB, you buy more storage iCloud.

• I have a lg 4 k tv (40 "40UH630V TV LG ULTRA HD 4 K) with HDMI 2. 0 and if I buy apple tv 4 can be used with HDMI 2. 0 port or do I HDMI 3 port to use this? Please help me

  I have a lg 4 k tv (40 "40UH630V TV LG ULTRA HD 4 K) with HDMI 2. 0 and if I buy apple tv 4 can be used with HDMI 2. 0 port or do I HDMI 3 port to use this? Please help me

  You can use it with your TV.