problem of delay FPGA can understand
Hello I have labview pci virtex 2 card in the computer and try to implement DMA from the host to the fpga (I use a clock of 200 mhz, which is the first of 40 MHZ with pll multiplier)
but every time I have an error of period not comply with the requirements of compilation happens that I can't understand how to fix it
I tried changed settings tick and insert the delay loop, but does not change the error
I have attached the results of error timming
can I get help on hw to solve?
Ghattas.Akkad wrote:
If a fast clock should not be better then a slower?
What do you mean by "better"? Faster, the clock, less you can do in a clock cycle. Your code uses a single-cycle timed loop, which means that the entire interior of the loop must run within a single clock cycle, and there is also a lot of logic in it to run at 200 Mhz. A fast clock is not better than a slowdown, if it is not possible for the code to run at the faster clock speed. Why did you choose 200 Mhz?
It is also unnecessary for the structure of the sequence, even if this is not bad no matter what.
Tags: NI Software
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Strange screen with acer Liquid Z220 shutdown problem
This has happened with my new phone smart acer Liquid Z220. Turning on the acer screen "android-powered" rises. The three logo (my provider). But then the screen turns white. However, the phone doesn't work and responds to the touch (without seeing m
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Is there a release OE for an attachment size limit? 10 MB?
Some time after 10/12/2011, it seems that my Outlook Express update can not send an attachment larger than 10 MB using the new ATT.net uses the smtp.att.yahoo.com my.yahoo.com, who is now married to AT & T site. I can send small attachments without