PXI-6653 DDS ClkIn reference

Similar Questions

• Override clock backplane PXI-1033 with clock OCXO PXI-6653

  I need a a more accurate 19.2 MHz clock of a PXI-6653. Supposedly, it is possible to replace the background clock of basket with a clock of the PXI-6653 OCXO PXI-1033. It is not clear to me how to do this. NEITHER literature suggests I may have need of a few SW. Thank you!

  OK, it seems to work now, thanks for the very useful comments. Someone suggetsed online (with a useful picture) to adjust the background rider of basket of 1033 'up' position... that opens the way for PXI_CLK10 - replacement of background clock of basket with the OCXO clock... Now I get what I was looking for, a (frequency) very accurate 19.2 MHz DDS clock.

• Pulse modulated CW with the PXI-5650 and PXI-6653

  Hello

  I'm trying to generate a signal CW of pulse modulated with the PXI-5650 as source RF and the PXI-6653 as the modulation signal. Basically, I'm trying to generate a simple radar waveform. It seems that it would be possible to use the synchronization Module (6653) to transform the RF output on / off on the signal generator (5650), but I do not know how to route the signals from one to another using LabView.

  Has anyone tried this or something like this before? Can anyone please offer some advice?

  Thank you!

  -John

  Hi John,.

  Reading your post, it seems you want to use your calendar and map of synchronization to the RF output power, in other words, on Off Keying. OOK modulation is a feature built into the 5650. For more information, you can navigate through the NI RF Signal generators Help for devices-RF signal generators > NOR -> NOR 5650/5651/5652 overview-> Modes of Modulation and simply click on the Modulation Modes.

  An example of this is found in the example Finder OR by navigating to the help-> find the examples in LabVIEW and then navigate in the Finder to example NOR material input and output-> Modular Instruments-> NI - RFSG-> signals-> RFSG 565 x Digital Modulation.vi.

  Kind regards

  Jason L.

• Cannot install OR sync and other on the PXI-8101RT

  Hi all!

  I PXI-8101RT + PXI-6682 and PXI-6653 + PXI-4462, PXI-1036DC + PXI-6143. I'm trying to install OR sync 3.3.5 and Multifunction DAQ & DSA 9.7.0 on 8101RT and get the message, that this components requires MIG string 2.3.0.

  What is the chain of MIG and where can I take it?

  Jury

  Hello

  What version of LabVIEW are you using? I noticed that NEITHER-SYNC 3.3.5 is supported for versions of LabVIEW 2009 and above.

  Try to navigate to C:\Program Files (x 86) \National Instruments\RT Images\NI-DAQmx, open the file nimigString.cdf with a text editor. If the version is 2.2.1, then change it to 2.3.0.

  If you are not able to find the previous file, try to install DAQmx first.

  Kind regards

  MCOTO

• PXI_CLK10

  I just added a PXI-6653 to my chassis PXI-1011, in slot 2 and trying to replace the basket bottom 10 MHz native PXI_CLK10 with high precision an OCXO in the 6653. The goal is to provide a divided (by a factor of 2) reference clock, which has the accuracy of the OCXO. I run this in LV 7.1, NOR-MAX 4.5 etc..

  The attached vi first connects OCXO to PXI_CLK10_IN, as a replacement for the native clock precisely this one. This part comes from "Clock.vi of road NO - SYNC"

  Then, from 'NO-SYNC Generate DDS Signal, fracture and Route.vi' DDS takes the exact PXI_CLK10 of backplane and brings it to CLKOUT full frequency, but also a more bass that is divided by a factor of two to the EPR of PFI0.

  The problem is that when I have the clock frequency to measure CLKOUT, there native backplane clock frequency (lack of precision), or approximately +/-4-5 ppm. I calibrated in fact my meter frequency by porting the OCXO out CLKOUT with the first vi, and it is calibrated to +/-0.5 ppm today.

  My problem would be with the PXI-1011 chassis compatibility problems? I read in another thread on someone with a PXI-1033, which had put the switch S1. I can't find any S1 or other switches config on this chassis.

  Someone at - he had similar experiences with the PXI-6653 and former chassis?

  Thanks in advance for your comments,

  Kurt

  Peter,

  Thanks for having a look at this. Yes, initially I brought OCXO to CLK_OUT, NOR - way Clock.vi SYNC and adjusted using the cal on the K & B (it has only 7-1/2 digit precision) for 10 MHz. This could serve as a basis to determine if I managed to replace the native frame PXI_CLK10 with the more precise OCXO.

  The fact that the attached vi gives a PXI_CLK10 read only 10,00008 to CLK_OUT MHz gives to think that my chassis is unable to accept the OCXO on the PXI_CLK10_IN line. Referring to the manual for the chassis PXI-1011, under Section 1, 'Reference of system clock', missing the verbiage I should be able to do this. Other chassis, such as the "1000/B, ' 1042 and even the ' 1010 have verbiage that PXI_CLK10_IN line can be operated by an external source." So, I suspect that an upgrade of the chassis is in my future.

  Thanks again for the reality check!

  Kurt

• Adjacent channel power ratio

  Hello

  I'll try to find measures PTA of the OFDM signal with 3 MHz of bandwidth using block ACP in the kit to SMT tools. But I'm out like NaN. Why is it so? Can someone tell me please?

  And I use NI SMU-5645R Transceiver.

  Thanks in advance!

  Looks like you can get the ACP SMT block NaN whenever steps out towards negative infinity. The way that the acquisition has been set up, I think that you receive an error on the fetch call, which returns an empty array of waveform, which adopted the ACP bloc. Which can lead to a negative infinite result. I have attached a modified project that works on my VST.

  Here's what I changed. First of all, I don't have a map of timing and synchronization, so I had to use scripts and a marker event to synchronize the generator and Analyzer. You can replace that with your overall software trigger code. Second, I made the acquisition changes I mentioned above: finite number of samples, endless documents, connected to the PXI trigger trigger 0 reference.

  Finally (and I don't know if this is necessary), I replaced your QI to spectrum VI with the SMT. the Spectra parameters are then passed to the ACP VI VI range.

  To do my VI properly, you will need to fit you your waveform. I used the script mode to synchronize the generator and parser which means that I had to use mode instead of the mode of power peak power average. Once you add your rear synchronization code, you can switch to the mode of the ARB and average power mode.

• task error DAQmx beginning-88709

  Hi all

  I have a chassis PXI-1045 filled with modules of the PXI-6120 S Series digitizer. I started to have problems when lance VI, receiving daqmx error task start-88709, indicating that a device has been removed or abandoned task. A clock device had been exchanged for the pxi-6653 to 6651 and re-configed at MAX (4.7). I found that text of presentation on this site about this was a problem common to all versions of DAQmx device before 9.2.2 drivers even if I had never seen him before the swapout of the card. 9.2.2 upgrade was the recommended fix that was done without problems. However, the problem persists. Now I also have a new problem on shutdown of a task, editing and restart the task. The clock and trigger signals are there... If these issues are linked and does anyone have a solution?  Thank you!

  lb

  
  

• Where slot - VI nisync?

  Hello

  I'm using Labview 8.6 on a PXI-1045 chassis, a synchronization PXI-6653 module, and a PXI-6552 HSDIO module.

  I want to use the CLOCK out of the 6553, but I can't find the Subvi PXI - 6553 NISYNC.

  Where are the Subvi NISYNC?

  I did a search for OR SYNC on the range of functions, and they aren't there.

  Thank you

  Roger

  I don't have the NO-SYNC in the Labview function palette, as show you.

  I already did a computer shutdown and restarted the computer after the installation of NOR-SYNC, and still there is no sub - VI NOR-SYNC in the palette menu.

  I'll try to uninstall OR-SYNC and re - install OR SYNC from the link you provided.

  Thank you

  Roger

• SCB-68 Terminal Block quick reference label does not match PXI-7831R pinout diagram

  I want to connect 3 analog inputs for the of IO reconfigurable NI PXI-7831R Module, use the connection series SCB-68 M block.  I noticed a gap between the analog inputs, shown on the terminal block of the SCB-68 quick reference Label and the analog inputs captured in the pinout diagram 0 connector NI PXI-7831R.  For example, the NI PXI-7831R connector 0 pinout diagram shows AI3 - and AIGND3 on the 29 and 30 pins, respectively.  The label for quick reference of SCB-68 watch GND AI and AI 3-pin 29 and 30, respectively.  There are at least six other cases where there is an incompatibility between the quick reference label and the pinout diagram.  Has anyone else seen elsewhere?

  Look at the label of SCB - 68 quick reference? M-series would be for the cards M Series DAQ devices where as the PXI-7831R is in the R series. You can see the difference here in this KB which has both the M series connector and connector M 7831R.

  I hope this clears up things!

  Greetings from Austin,

• The reference output analog of the PXI-67xx (AO GND) isolated or linked to the mass chassis/installation?

  I am trying to simulate a radiation of 3 mV/V power pressure transducers (excitement is + 10V, full range should therefore be 0mV at 30mV).  I am looking for a PXI analog output device high number of channels (PXI-6723, possibly) who doesn't have the down side of the analog output channels linked to the land of installation (differential channels of AO).  The plan was to use a voltage across the divider circuit of +/-10V output card AO to +/-50mV.  I use a card AO 16-channel, 12-bit which has all the Commons AO related to the mass of the PXI chassis and Earth installation.  The DC of the signal part I want it, but there are about 80-100mVpp of noise (from the ground connection) riding on it.  I also tried a PXI-6115 card we had at hand and its reference AO are related hard chassis-same result with the noise of the Earth.  Is PXI - 6723 AO GND isolated from the land of the chassis/installation?  Even if all GNDs AO are shared on the Board, this solution should be much better than having a noisy ground reference.

  Any ideas?  Alternatives to simulate a floating, the millivolt output device?

  Thank you!

  The reference of the AO of the 6723 relates to Earth; pages exit track to track analog insulation research, only a handful of AO devices have an isolated field (the business is a low channel count).

  -Ciao

• The streaming of data in c (PXI-5421)

  Hello

  I do the data streaming in C by PXI-5421 follow this instruction: http://zone.ni.com/reference/en-XX/help/370524R-01/siggenhelp/streaming/

  Here's my psudo code:

  1 set the amount of memory shipped to use for streaming

  waveformSize = 1048576;

  short * CurData [16];

  checkErr (niFgen_init (resource, VI_TRUE, VI_TRUE, & vi))

  checkErr (niFgen_ConfigureChannels (vi, ChannelName)); ChannelName = '0'

  checkErr (niFgen_ConfigureOutputMode (vi, NIFGEN_VAL_OUTPUT_ARB));  //Arbitrary mode is used

  checkErr (niFgen_ConfigureSampleRate (vi, SampleRate));   Rate of sampling = 40e6;

  checkErr (niFgen_AllocateWaveform (vi, ChannelName, waveformSize, & wfmHandle));  Allocate memory for broadcast borad

  2. identify the waveform streaming

  checkErr (niFgen_SetAttributeViInt32 (ChannelName, NIFGEN_ATTR_STREAMING_WAVEFORM_HANDLE, vi, wfmHandle));

  checkErr (niFgen_SetAttributeViReal64 (vi, VI_NULL, NIFGEN_ATTR_STREAMING_WRITE_TIMEOUT, 10.0));  Set TimeOut = 10 s

  3. fill the waveform continuous initial data

  for (j = 0; j<>
  fread (CurData [j], sizeof (short), waveformSize/16, PlayedFile);  Read data from my saved file
  checkErr (niFgen_WriteBinary16Waveform (vi, ChannelName, wfmHandle, waveformSize/16, CurData [j]));
  }

  4 start generating the waveform

  checkErr (niFgen_ConfigureOutputEnabled (vi, ChannelName, VI_TRUE));
  checkErr (niFgen_InitiateGeneration (vi));

  5 write a waveform data block. (Optional) Monitor available memory that generates the waveform

  {}
  niFgen_GetAttributeViInt32 (vi, '0', NIFGEN_ATTR_STREAMING_SPACE_AVAILABLE_IN_WAVEFORM, & FreeSpace).

  {if(FreeSpace>=waveformSize/16)}
  fread (renewData, sizeof (short), waveformSize/16, PlayedFile);

  checkErr (niFgen_WriteBinary16Waveform (vi, '0', wfmHandle, waveformSize/4, PlayData));
  //}
  } while (1);

  I properly generate first 1048576 points of data. However, I'm stuck in writing new data in my space of memory onboard.

  The error message space in continuous waveform has not become available within the specific period, and appears after 10 sec which is my time-out period.

  If I check my available space via the property NIFGEN_ATTR_STREAMING_SPACE_AVAILABLE_IN_WAVEFORM, it never increases.  Did I miss something? Can I work in arbitrary mode for data streaming?

  Any suggestion is appreciated. Thank you!

  Looking at the example LabVIEW/CVI, it seems that you are on the right track.

  If you remove the Do / While loop, do you still 1114112 samples? In other words, samples of 1048576 (1048576/16)?

  What is the value returned by ' niFgen_GetAttributeViInt32 (vi, '0', NIFGEN_ATTR_STREAMING_SPACE_AVAILABLE_IN_WAVEFORM, & FreeSpace)? "

  I have attached the CVI example in this post. It has many additional functions that change the GUI of the CVI, but ANY function calls should be the same. Is the only thing that is considerably different that they set a number of rehearsals and use unique relaxation mode. I would go ahead and change your code to be similar in order to ensure that it is no hardware problems. Then I would try to generate and disseminate a sinusoid first before trying to use your file. I hope that we can refine all the problems.

  Jason L.

• using the reference find send me modal autoguiding errors

  Hello

  We have an NI PXI-7354 controller not to not/Servo control a player Primatics PN 0-7205-0012 2-axis, 2 rotating turntables Micos DT-120 running.  Recently we know modal errors during autoguiding'-70119 (NIMC_limitSwitchActiveError), move the desired can not be completed, because the entry limit is enabled in the direction of the market. »

  This system has worked for years, a dthi sjust began to appear on homing which occurs once a day.  This happens when the move to find reference goes to the opposite limit, because it is programmed and configured for this purpose.  It then performs a small movement to the front, and then this error occurs.  Now, I understand that this is part of the command search referrer.  It seems as if grace to carry on the switch, or perhaps in the stadium itself when it moves forward to the switch in an attempt to approach of the reverse switch slowly with specific accommodation, that is not actually the switch, and the movement fails.  It is not easy for me to change the switch on the scene, but it can be done.  I wish I could say find reference go further forward, then he actually gets the switch before it he comes again.

  So, I guess that's supposed to happen

  1: the reverse of the race during the domiciliation

  2: switch hits

  3: small forward

  4: move in the opposite direction

  5: Press the switch - success home

  Step 3 moves a pre-programmed amount?  If so how can I change?

  Alternatively, step 3 move until the limit becomes inactive, in which case I'm having bounce or noise on my switch entry.

  I tried to adjust the position of the switch House, there is a small amount of adjustment possible.  I also changed the speed of the stroke finding reference to 50000 c/s 25000 c/s and I have yet to see another failure, but I am not convinced that this is the best and most permanent action plan.

  Any help would be greatly appreciated.

  Have you had a chance to watch http://www.ni.com/product-documentation/4190/en/ ?  Your thoughts sound than the limit switch is always on even after step 3, which must turn off the switch.  Looks like that means to get around this issues is perhaps to change the direction of final approach or the speed of movement.  From this page on the limits to find: http://zone.ni.com/reference/en-XX/help/372134F-01/ni-motion_help/findforwardandreverselimits/ it seems that any direction final approach should work, because in step 3, he should see the switch disable before approaching again, but maybe give changing the final approach response to try.

• How to delay a PXI-5122 trigger before routed to string of PFI

  Hello world

  I use a PXI-5122 in a PXI chassis. I want to synchronize with two external devices. The first will send a trigger (with a 10 Hz repetition rate) for PXI-5122. Then PXI will generate a trigger (with a constant delay) in the second.

  It seems that I need to generate a trigger, then export this trigger to PFI 0 line, but I do not know how to delay triggers with a timeframe of 4µs. I read that there is a slight delay between a trigger on the PFI and the first sample. And the length of the cable is also an important factor to consider.

  Could someone give me some suggestions?

  Wednesday,

  Thanks for the drawings, that helps a lot!  Somehow, I see this work (how to set up the scanner):

  1. set up the record length to be 12us (4us trigger samples, 8us after outbreak).  If the sampling frequency is 100 ms/s, that would be a record length of 1200 samples.

  2 configure the position of record reference to 33%.  That's how the digitizer breaks 1200 400 samples according to trigger before triggers and 800 samples.

  3. configuration of triggering immediate reference.  This will allow the acquisition of trigger the moment she gained 400 before triggering samples.

  4. export the "reference trigger (Stop)" to send to Device_2.  This output pulse is of variable width, so if you want consistency, you will need to the Device_2 trigger the rising edge of the pulse, did not not fall m.  Once 400-pre-trigger samples are acquired, this impulse will be sent, and then the scanner will be immediately habitable after initiation of sampling.

  5 configure the trigger of the entrance of Device_1 (10 Hz trigger), as the 'Advance trigger' and 'Start Trigger'.  This will make the digitizer wait this impulse to start sampling before the next record.  We set up, the relaxation of beginning to the 1st record and the trigger in advance for all subsequent records.

  This facility should allow a pretty decent timing, but please test to be sure that it will be sufficient for your application.

  Kind regards

  Nathan

• Calculation of the frequency of real output of a PXI-5402

  I have a card PXI-5402, sitting in a high chassis. I'm only interested in the sine wave output at frequencies up to about 10 kHz. I know that it is possible to request an output frequency and then interrogate the acutal output frequency but I prefer to be able to calculate before hand. All I can find in the literature is a figure of 0.355uHz for the frequency resolution.

  Is there a better description of the frequency resolution? If this is not the case, the resolution is exactly 0.355uHz or is it an approximation (to 3 significant digits)?

  This webcast is a great way to learn the process including the NI 5402 5406 OR exploit to generate periodic duty: http://www.ni.com/webcast/75/en/

  The 0.355uHz value is a theoretical value of the frequency rate achievable depending on the size of the accumulator Phase and clock frequency. It's the closest thing I can find on ni.com that you can use to calculate the value: http://zone.ni.com/reference/en-XX/help/370524R-01/siggenhelp/ni_5401_11_31_frequency_resolution_and...

  According to me, Fc for the NI 5402/5406 must be 100M and the size of the accumulator is 48 bits. Frequency resolution so = Fc / 2N = (100 × 10 ^ 6) / 2 ^ 48 = 3.55271368e - 7

  Keep in mind that the device has a VCXO frequency accuracy specification of + / 25ppm, if you have no PLL block him to a better source.

• Change the topology without reference to closing

  Hi all

  I was wondering if I should be able to change the topology of a MUX (reset) without closing the reference?  I have an application that performs a loop on the base initialization, connect, disconnect the sequence for functions OR-Switch and the topology changes for each loop.  I think that my reference is lost, because it becomes invalid after several loops.  I have to close the reference before I reset with the new topology?  I'd rather not have to close every time, because I 'cleansing' steps that close of references outside of the loop. In collaboration with the PXI-2527, LV 2013 and 2013 TS.  Thanks in advance.

  GSinMN

  Ali GSinMN,

  This knowledge base Article should answer your question. The last line reads, "during the change of topology, you close the current session if one is open and reset the map with the selected DriverSetup new.»