Q on the timing in VI and Subvi loops

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• Simultaneous use of flex pitch and the "timing" on the same region?

  Is it possible to edit a region in 10 with the two flex pitch logic and timing? When I toggle between modes, I get a message that informs me that pitch adjustments will be suspended. If I put the pitch of the notes to something way off - to check it out - it seems that as soon as I switch to flex pitch in calendar mode, pitch adjustments are ignored. Is it possible to have both at the same time? Workaround is bounce calendar settings in place then the correct pitch. Is this the best way? The only way? Any information would be appreciated. Thank you. -John

  IF you use flexible hours first then flex pitch your flexible hourly landmarks remain intact. In pitch flex mode you can select to the end of a note and drag to the right or left and upwards or downwards. So you can bend the pitch and flexible at the same time, but only when there is an event of note.

• What is the interaction between appellant VIs and subVIs using VI Server?

  I am student at the CLAD and one of the lines in the document preparation or here is the following:

  What is the interaction between appellant VIs and subVIs using VI Server?

  I know how to use the function "Call for reference" to call a VI, but not necessarily a Subvi. I thought a Subvi is always loaded with the calling VI and has nothing to do with the server of VI. What Miss me?

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  I think that this article will clear up how the VI Server works with subVIs called statically or dynamically.

  Call a VI by reference

  Best regards

• Sequence structure flat inside the timed loop and execution order

  I have some problems trying to implement a flat sequence structure when you use a loop timed on a target of cRio VI

  I tried with or without the while loop around the structure of sequence flat, and I also tried to replace the 'Non-deterministic loop' with a timed loop

  The problem is that the program seems to run only once, then get stuck somewhere

  I am writing a program that performs the following operations as soon as possible:
  1. read the Pos_MC of entry on the FPGA
  2 send the value of Pos_MC to the VI target (on cRio CPU)
  3. calculate a value of output based on Pos_MC with a PID block ("exit PID')
  4. send 'PID output' to the FPGA
  5 write "PID output" analog output "MOOG".

  In addition, I want the program to return the measured value "Pos_MC" to a host VI for the recording of data

  So that the output of PID is calculated and sent to the FPGA as quickly as possible, I placed a flat sequence structure to ensure that it happens before you send the output to the nondeterministic loop for recording data

  Also, I want the digital input 'Stop' to be able to stop the loop deterministic (the timed loop)

  I read much more entries than that and the help of several PID and exit, but I rewrote the code for a single entry and exit to make it easier to illustrate

  Screenshot of the code is shown in 'target code.png' and 'fpga code.png.

  The VI themselves are attached in the next post (cannot attach files of more than 3)

  Question 1:
  Any advice on how to get this race? Thank you!

  Question 2:
  Is also my correct understanding in that, using this structure, each 0.9ms (fpga loop time) comes the following:
  1. the input ("Pos_MOOG") is read on the fpga
  2. the production of PID is calculated on the cRio with some delay to computation (for example 0.1ms)
  3. the output of PID is then written for analog output "MOOG" in all about 0, 1 - 0.2ms
  4. the FPGA program then waits until 0.9ms spent and repeat the process

  As opposed to the next pass whenever performing a loop is started on the FPGA:

  1. the FPGA reads the input and written on the output (the output of the execution of the previous loop PID)

  2. then the entry is sent the cRio, PID output is calculated and sent to the FPGA

  3. the new release of PID is maintained until the next time through the loop

  Thank you!

  PHG wrote:

  Thanks for the input guys, any advice as to how I could get the feature in scenario 1?

  I still say that the best route is just putting all the logic of the control in the FPGA.

  Other alternatives include 1) the use of DMA FIFO sedn data back or 2) use interruptions so that the FPGA code can not read the output level until the RT.

  DMA FIFOs are usually very limited, and I would not use them in this situation since I belive said it this code to do for the many outputs.

• Why the timing information not disappear when I switch off sync in my office?

  I'm at the office, in my work and I disconnect from my account synchronization to work and I want to connect to my personal account, but I can't because the timing with the first account information have not gone and wil be merged with personal information.

  Sync is not intended to be used in this way. Data that is synchronized is not a temporary view, the data is copied in Firefox on the device: the data do not disappear when you disconnect fron one account synchronization or close Firefox.

  You have to work and personal accounts of Sync thru having two distinct profiles.
  https://support.Mozilla.org/en-us/KB/profiles-where-Firefox-stores-user-data
  https://support.Mozilla.org/en-us/KB/Profile-Manager-create-and-remove-Firefox-profiles

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• Enable/disable or change the "timing" on the backlit keyboard

  I love the backlit keyboard, which was a key factor for buying the P750.

  But is it possible to change the State of the backlit keyboard?

  I found that the economic mode turns off the light, but is it possible to turn it on continuously - or change the "timing"? In my opinion, that he died too soon.

  Please open Toshiba Assist > Optimize > HWSetup and you will find all the options related to the keyboard backlight.

• How to create the hierarchy without creating a Subvi files

  Hello

  I have an existing LabView program that uses blocks of Subvi.  I want to change it so that I can't copy files Subvi (when I transfer the program to another computer).  The goal is to have a single file/program that I can copy, paste, and run on other computers.  So, I want to know if there is a way to create the hierarchy without creating a Subvi files or how to integrate the Subvi in the program.  My program and Subvi files are included here.

  Thank you

  Rocky

  You can create a version in an executable file.  It would be the most common way if you insist on having a single file.

  You could also build a source distribution in a zip file.  Then you just copy and paste the zip file and unzip it anywhere where you want.

• pass-through of a Subvi to the next level with continuously running loops

  Hi all

  It is a very simple question, for some reason, data available as a Subvi indicator doesn't it up level vi. I think it might be something to do with the while loop I use, but I cannot understand, any help will be appreciated. I don't think I quite understand how data comes out of a loop constantly running.

  GPSdisplay runs a driver called GPS.vi (im not worried for my event structure immediately, which could be bad, but I am yet to test this bit yet) 1 probe should have the values of GPSCluster

  

  Loop in GPS.vi. GPSCluster (sensor 2) is updated correctly

  

  I can't work on why the data is not passed to GPSCluster at the top of page vi

  

  Hi bennymacca,

  I think that you are on the right track with a FGV. You can do quite easily with GPS vi you have.

  Before going further, your GPS while loop will return only the last reading and because the Boolean value of "Read" output state is set to FALSE, it will not stop. You see it out at all? The logic, I read, once entering this while loop, that he will not stop until said.

  There are 3 options you can try.

  (1) use a FGV, because you are looking in. To do this, you need to change the boolean TRUE State and set records in the GPSCluster - to analyze the information around, holding each time the vi is called and you leave. Outside the while loop you will thread to the top of the cluster to the indicator that you want to collect (OR you can have it inside the case statement where you read - be careful here, if).

  (2) in the main code, above the frame of the sequence, you can place the GPS vi while loop (the ' read' a), given the State of the boolean connected to a local variable of the Stop button. This while loop will start depending on how feels LV, wire, one line error for the two while loop and Frame (indicating that the two are to run in a parallel mode), OR you can put it in a case statement and say 'go' when you want to start playback. In this while loop, you can then copy the data to read directly in your variable Cluster that it is generated.

  But with (2), you move yourself away from the purpose of the GPS vi, which would be to bring all the features of the GPS functionality in a vi - which is a good idea.

  (3) put a condition on the State of the Boolean case "Read" statement - just make it TRUE when you want to stop reading the data (do you have a time or a condition, you can check here?). Even by doing this, you would / may still need to shift on your lease registers loop to keep the data for each iteration.

  I hope that all of this help. See you soon. David.

• Analog control over the timing of myRIO MSP?

  Hello

  I'm new to myRIO and just got my.

  How do you set the rate for similar samples of the port of an MSP myRIO?

  For example, I would like an analog stream output 200ksps.

  Place the block of OUTPUT ANALOG in a timed loop and runs only gives an output of 6.3 kHz frequency. (measured at the ao1 using a scope)

  See the attached file.

  I incorrectly use the timed loop? (.. .havent used before)

  Or myRIO does needs some extra configuration?

  Thanks for any help to what appears to be a very simple problem.

  See you soon.

  Hey, Carloman.

  In this case the speed is limited by the software (OS, background process and especially the code LabVIEW) running on the ARM processor on the myRIO.  200 Ksps specification is for the hardware.  If you need to write this young, you can use LabVIEW FPGA to write data.

  One of the reasons why it is difficult to reach the 200 Ksps output rate of the side RT is because each iteration of the loop produces only 1 sample (the FPGA is configured for the only point of exit... a sample at a time).  The perfect way to generate samples on the side RT and to write data to 200 Ksps is to build several samples each loop and use a FPGA personality that supports analog output buffer in memory.  This allows to generate N samples each iteration of the loop and then send samples to a FPGA (FIFO) buffer that implements buffer and copy the data.  I believe that it is coming in a future update.

  For now, you can implement this architecture by creating a custom FPGA personality or you could do everything in LV FPGA.

  Let us know if that makes sense.

  Thank you!

  -Sam K

  Hacker of LabVIEW

  Join us / follow theGroup of pirates of LabVIEW on google +

• Rate the triggered loop of the timed iterations of TTL

  Hi all

  I have a camera control VI that awaits the shutter of the camera TTL information and use it as a source of synchronization for a timed loop. In this timed loop, the camera is read and analyzed. Program should respond as soon as possible a new image and that's why I put the timed loop to "Throw missing items" so that it does not seek to catch up (events im trying to detect is quite rare and last several frames).

  The problem is this: when I put the camera for a certain numebr of frameworks (e.g. 10,000) sometimes due to discarded frames ever loop iteration number the last number of frame expected and do not remove (it remains to 9.998 for example). I noticed I can stop it by deselecting "maintain phase." However, it is clear to me what happens exactly with these settings in a situation of TTL triggered.

  It is true that the loop passes the new data directly but starts the next loop the correct number of iteration (+ 1)? Or something else happening?

  IM grateful for any help!

  Dear j.win,

  If you deselect the option 'Maintain the Original Phase', in fact you never will reject any iteration, whatever the value "Discard missed items." On the contrary, the loop will try to catch up the iterations of the end.

  Use of a source of external synchronization (for example your TTL) instead of a source of internal synchronization does not change. You can use the 'period' entrance (dt) of the loop timed to specify when the loop is supposed to go (the unit is the "ticks" in the case of an external synchronization source). A value of '1' means that test loop to iterate over all the graduations of external synchronization source. If for any reason any iteration lasts longer than that, you'll have an iteration "end". Also with a value of '1', it is not possible to change the "phase", then the parameter "Initial Phase to maintain" will be defined only weather or not ignore you the iteration. If 'Maintain initial Phase' is set to false, the loop will run immediately after an end iteration to run always, but a little of the latter. If the 'Maintain initial Phase' is true, the loop will run immediately after an iteraion end if the option 'remove point missed' is false otherwise the loop will jump the iteration.

  It's more clear now?

  Kind regards

• Difficulty to read the instrument of series and acquisition of data simultaneously.

  Greetings,

  I have some trouble getting my VI read from my data acquisition and instrument of the series at the same time.  If I run the Subvi simultaneously (i.e. subANG runs in a window and subVEL is running in a second window) both return the correct values and behave as I expect.  However, if I call the Subvi in a society mother VI and try to run them both in the same loop structure subANG gets stuck and won't be reprobed with a signal change.

  I also tried to use a stacked sequence or plate to separate the execution of subVEL and subANG, but I still get no response to subANG.

  The point is is that, if I run Parent.VI in a single window and then creates a copy of subANG (call it '--copy' or other) and run it in a second window, Parent.VI behaves properly and will update the readings as they appear in '--copy '.

  I enclose 3 files.

  (1) subANG.VI - this bed an an inclinometer RS232 signal.  The signal is refreshed every 10ms or more.

  (2) subVEL.VI - this bed raw tension of a channel on the acquisition of data, calculates the average then that converts into a pressure difference and finally a speed based on the pressure and temperature inputs.

  (3) ParentVI.VI - they simply call and displays the Subvi

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• How can I interact with mainvis and subvis without closing any of them?

  I have a mainVI which opens a Subvi perfectly and I m using the "VI Open reference' & the 'node of reference VI to call' to run the Subvi. However, once I open the Subvi and it s running, I can´t do something with the mainVI. The only way to interact with the mainVI new it s closing the Subvi, I want Don t that happens because I need the two work together and interact with both at the same time.

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  Make sure that the property of Subvi is not floating or modalvalue.

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• Pushing the control captions into a Subvi

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  Any help is appreciated!

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• Impossible to click on the buttons for the timed loop.

  Hello!

  I have a loop that is timed with a pace set by the user. And when the loop is running, I can't push any button of my GUI to stop it...

  I have to wait until a mistake or I stop the race.

  I can't put the diagram is too big and I think I don't have the right, but you have ideas?

  Ask me for more details.

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  bejard wrote: timed loop is just in a structure of the event and I put 10 ms or 100ms.

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• How to read the color table in a subvi?

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