Table of distribution of the FIFO

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• "Distribution of the Proxy table" featured ACS 5.2?

  Hello!

  Is it possible to have something similar to the table of distribution of proxy 4.2 ACS ACS 5.2?

  I need to authenticate my users with ACS against AD and let guests to authenticate to external radius proxy.

  4.2 I manage it with the table of distribution of proxy: the suffix @ourdomain to my ACS and the rest points goes to 2 radius proxy servers.

  5.2 can I define a strategy of selection of the Service with the Service Type 'Proxy RADIUS' but I can not set a rule to test against a domain or a user name and based on this result authenticate locally or send with radius proxy servers.

  No idea how this can be done in 5.2?

  Thank you

  Wolfgang

  I think that can be done so driven off the username in the RADIUS request

  (1) create definition of RADIUS proxy servers:

  Network resources > external RADIUS servers

  (2) create the proxy service:

  Access policies > access > create:

  Type of Service selected user should be "Proxy RADIUS" and select RADIUS server in option 1)

  (3) create conditions for the custom user name attribute:

  Elements of strategy > Session Conditions > Custom

  Dictionary should be "RADIUS-IETF."

  Attribute should be "user name".

  (4) change the selection of the service policy.

  Reach:

  Access policies > Access Services > Service selection rules

  Press 'Customize' and select 'User name' condition that was created in step 3). Press OK

  Now to add a rule to check the username and pass them on to the proxy server required

  For example the condition: "" If the username ends - with @ourdomain ".

  result: the service Proxy created in step 2)

• SMU FlexRIO DMA FIFO host read the FIFO overflows broadband bandwidth/DMA issues

  I'm working on an application that uses 2 modules FlexRIO, and 2 LVDS digital I/O adapters.  I'm driving each of the SDC A/SDC B ports on LVDS 16-bit data at 50 MHz adapters.  The FlexRIOs are expected to receive the data and write down them on four targets-to-host DMA FIFO (one per connector SDC), or two by FlexRIO.  The host reads the FIFO and brings together a series of tables each FIFO output 2D.  Ultimately, the individual tables (we're each a quarter of single image) will be assembled in simple images, but I haven't gotten that far yet.

  The duty cycle for the data is about 80% (in other words, I'm only transmit data to the FlexRIOs 80% of the time, the rest of the time the transmitters are disabled), so the flow is about 80 Mbytes/sec/port total invasion, or 320 MB/s on the four FIFOs DMA.  I find that the acquired data gaps sometimes inside that line up along the length of the material part of the DMA FIFO in FlexRIO modules.  In other words, if my memory FIFO DMA are set to 65535 length, I'll see a break in the data acquired at the word of data 65536th.  Data is a waveform of sight, which is essentially just a counter, so it's easy to see the break in the model.  For the words of first 65535, adjoins the data, then from Word 65536 model is discontinuous and starts counting again from there, contiguously.  At the beginning of the acquisition, the FIFO is erased: the beginning data read from the FIFO is always aligned correctly, so I know that the process starts at a good point.

  The error is not always the case: sometimes I get continuous data through the point 65536.  In addition, the error occurs independently between the four FIFO: on a particular race, a FIFO could have data of interest and some bad.  Rarely, all four FIFOs have good data.

  The fact that the gap of the configuration is to the point even the depth of the FIFO DMA tells me that fills the FlexRIO FIFO, the FPGA hardware without the system managing to move to read, which means that the data gets dropped during the period that the FIFO is full.  Then transfer to the host comes into action, there again is the space in the FIFO, and the data is once more contiguous in FIFO memory for a large amount of data (I have not yet tried to locate a second gap in the data of a single acquisition).  It seems therefore that the host doesn't have enough bandwidth between the FlexRIOs and the host of RAM to prevent the filling FIFO, or comes along some software process on the host that is temporarily stop the ability to instantly transfer.

  Are at - it a specification for the SMU flow system that would indicate that we are trying to use too much bandwidth?  Or are there priority controls on DMA FIFO that would allow us to raise the priority of the FIFO transfers as they are guaranteed to go in preference to other system tasks?

  System Specs:

  SMU-1075 chassis

  SMU-8135 CPU

  2 SMU-7962R FlexRIO modules

  2 digital i/o modules of NOR-6585

  LabView 2012 32-bit SP1 version 12.0.1

  A suggestion of an applications engineer of NOR and some experimentation has solved the problem. It turns out that I was calling the method FIFO of DMA stop just before the outbreak of the transmission of the data via a control for the FPGA FPGA VI. I did this in order to clear the FIFO before you begin data acquisition, but I didn't know that this method disables also transfer data between the memory FlexRIO and host. Following this call, I trigger the FPGA code to start filling its FIFO and then begin reading. Calling the Read of FIFO of DMA apparently light up the transfer back, but it seems that the host VI has been randomly slow down enough to move to the bed such as filling the side FlexRIO FIFO and dat would be lost. I changed the host VI to insert a FIFO method call start before the trigger for the FPGA signal, and the problem is now gone.

• How can I display the table of contents for the iPod Touch to 6

  When I opened first of all iPod Touch Users' Guide, I used the table of contents (TOC) to locate and access sections in the manual. But, after looking through the manual for awhile, I tried to return to the table of contents, but it wasn't there! I have tried various things to see if the table of contents are being hidden, or if in some way, it has been deleted. Anyone can shed light on this mysterious event?

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  TT2

• User Message interface help - table to send to the user through ActiveX interface

  Hello

  I asked a similar question before, but now I'm having problems trying to get a table in the user interface via the mail user interface. I am my code TestStand, I have an expression to send a picture that is as a container of table of FileGlobal to the UI as such:

  RunState.Thread.PostUIMessageEx (UIMsg_UserMessageBase + 2, 0, "", FileGlobals.DataRead, False)

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  Is attached, the UIcallback, a picture of the table on my user interface and control

  
  

• FIFO.config - 61206: but the name of the FIFO is

  Hallo,

  I am relative new to cRIO and I became a mistake the last time, I've compiled my FPGA.

  Description of HW

  • cRIO-9035
  • 4 x NI9229

  Description of the software

  • FPGA: I have 15 DMA FIFO (I can do this according to this document), which send asynchronous messages on each FIFO (see the joint photo)
  • RT: I get this message and I store them in a PDM file

  Problem

  • FIFO. Configure or FIFO.start gives me "error-61206." This error, as shown here, means that there is no such thing as the name of the FIFO. But as pictured there. I don't know what happened. Is the first time I get an error like this.

  For your impeccable support, I'll tell you ' thanks!

  Carmine

  I found the problem.

  Only really used FIFOs on FPGA can be configured.

  If you declare a FIFO and you won't use it on FPGA (for example to do a test of part of your project) you need to remove from code RT parts where you configure, start closed ancd FIFO.

  Thank your for your attention.

  Carmine

• sorting table, how to get the new index of the last value?

  Hi all!

  I use a Subvi, which adds a cluter of the parameters to an array and then sort this table by one of the parameters in clusters.

  It works very well, with examples, that I found in this forum

  but now, I would like to know if it is possible to obtain at the end of the new cluster index first added.

  See attached VI

  Thank you

  You take the size of the table and insert the new element to this level is anything other than the table of construction and a simple construction would do that.

  In your question, I assume you're asking on the index of the item that you inserted after the sorting of the table, right? In this case, you can compare the cluster element that you introduce to the initial with the cluster table you get after a sorting of the table. This will give you the index of the item that you insert at the start.

• Accuracy of size for the FIFO DMA

  I started to develop a code of RT for cRIO with DMA FIFO function application. A few questions have very fundemental

  fluctuated around in my mind. The FIFO DMA is supposed to be made up of two components FPGA)

  side & on the RT side).

  1 the total THAT FIFO composed of FPGA side FIFO + RT side FIFO?

  2. the FIFO of DMA size that I put inside the FPGA target in the Project Explorer refers to what just FPGA)

  FIFO or Total size)? If it's just FPGA side FIFO, how big is the RT side FIFO together (is

  It automatically assigned by RTOS free memory function)?

  3. in addition, size defined programmatically by using DMA-configure is the equivalent of setting the size

  in the Project Explorer?

  4. Finally, how can I estimate the maximum size of the FIFO that I am allowed to use?

  Thanks in advance for any response.

  Hi Shiva419,

  1. Yes, at least a DMA FIFO has these two sides

  2. I just read in another reply that the size you set for the FIFO in the Project Explorer is the size of the FIFO on the side FPGA. The size of the FPGA on the side of the RT is much larger (default is 10000 items).

  http://forums.NI.com/NI/board/message?board.ID=280&message.ID=5108&query.ID=99697#M5108

  Mandar-

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  Thank you

  Matt

  And yet anothr approach...

  Right click on the bar of > Options to fill > maximum fill.

  

  The fill color of the same color as the background color, then make the background color transparent.

  Drop a box of color BEHIND the bar and the size correctly.

  He has this strange background 3D with flat bar, but what the Hey, his relatives. If its important a custom color box.

  Ben

• Read the CPU hits 100% in the FIFO usage

  I have a PC in real-time with a card of RIO 7833R. I write the values that I read a microphone in a FIFO at a sampling rate of 4 kHz.The length of the FIFO is 2048. The PC in real-time, when I call 'FIFO read' function to read say 400 data samples, the use of CPU time real PC hits 100%. Why is it so? The function 'Read FIFO' is placed inside a while loop.

  Thank you

  Prashant

  Hi Prashant,

  Reading the FIFO is a method of querying, so if the number of elements specified to read are not available when the method is called, it queries the FPGA until they are.  This causes the CPU to 100% usage. You can find more information on this subject and a way around this here.

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  Use the property "Change Position".

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  Use the Array function to build with just the single entry.

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• Table 3D: cannot replace the 2D subset?

  Hey guys,.

  I discovered a rather strange event (if any). In debugging my code, I stumbled upon my function replace table subset to find that it was the source of my frustration. Either I don't understand how it works for 3D arrays (I use it a lot for 2D, 1 d) or there is a bug. I have attached a picture of the code examples here. I can't replace a 2D picture into my table 3D. I would like to take a page from the 3D and replace it with a page of update / different. The example image is sure to strongly the oddity.

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  Regardless of the size of the input array, the result of the table replace never increase the number of items.  You try to grasp the first page, add a line, then replace the first page.  The result is that the replacement is cropped to the initial first page size, if you have a developed NOP (no operation).  Move the entries in your table to build on it and see what happens.

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• 2D table are displayed in a table, 1 row at the same time

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  Yes.  Put your picture inside the loop indicator.  Use the Array function to build to build your table.  Insert the table into a shift register.

• Table of references to the different types of performance issue

  Hi all

  See the attached code. I use a reminder VI and must pass a few references via the user's settings. I use a table.

  This is to avoid the constraint (should I care?), I type cast to more of a generic class, then in the callback function, go to a more specific class. (What is the best way to do it?)

  As you can see, even if, for some reason, almost all the nodes property are reading as variants, forcing me to use data Variant, which seems inefficient. Why is this the case? If I type cast to a Boolean, the value should be a bool... Why force me to use for the data range?

  Is there a better way to do this? Thanks for the comments.

  If you use a cluster of istead of a table, you can maintain the rigour of the reference.

  The reason why you have found variants is that you don't are not cast the ref to the same type. Try...

  Hand, create a strict constant of the wire Ref. Make slide a constant in the call back VI and use it when you launch as more specific. Property nodes you adapt to the specific data type they have in hand.

  Note:

  You can also create references of the appropriate type by dragging the appropriate type of control in the Ref control and it will fit.

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