The broadband divide

Deal all,

I develop a VI FPGA to calculate the least quadratic average, over 19 samples acquired with 9223 module e/s OR cRIO-9012 controller and chassis cRIO-9118. You can see that my code in the LMS snipped attachment.

I have problems with understanding the setting of flow to the section for configuration of the function execution Mode to divide broadband within a SCTL. When I set this variable to 1 cycle/sample, it seems to me that the correct results after the function of division broadband are coming after the latency time of the function. Thus, for example in this case after 30 cycles. But when I put the possible maximum value, in this case 29 cycles/sample, I never get a correct result of the division, and the result is always on the increase until the maximum number that goes to zero and start to increase in the same way. So I really do not understand this function.

Can someone please give me more information about the function broadband divide? At least more information about the flow setting.

Thank you very much.

Kind regards

Nikola

Hello Nikola,

You need 30 cycles to get a valid result - no matter what bitrate is defined. When you set the control to the value 1/cycle you can subscribe a value to each cycle. The calculation is in pipeline and intermediate results are stored in shift registers.

When you set 30cycles value, all 30 cycles only you can feed a new value. The advantage is, it costs less resources that piplines are less necessary.

I think that the valid output is not wrong all the time, it is true once every 30 cycles and miss you maybe looking at the face before of the VI. Use the "valid output' 'ready for the entry' control of the power/reading of new values. Alternatively, you can use 1cycle by value if you have resources left on the chip,

Kind regards

René

Tags: NI Hardware

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