Then as the loop timer Timing vannes_ouvertes. Elements

I would like this while loop to iterate through every second. But it seems that he doesen't recognize the loop timer. What's wrong?

Just found the article to help talking about it: Debugging of FPGA screws using Mode Simulation (FPGA Module)

At the bottom, it says:

Understanding simulated time on the host computer

If you use some FPGA resources and you run the FPGA VI in simulated using I/O simulation mode, the resource uses simulated time rather than real time. Simulated time could be faster than real time according to the number of events that occur during the simulation. For example, if you add a waiting VI (simulated time) for the schema and set the timeout to 1000 ms, LabVIEW does not attempt to delay a second of real time. Instead, LabVIEW delays as long as necessary before performing the next action scheduled in the simulation.

The following resources are using the simulated time on the host:

  • Then the loops

  • Single-Cycle timed loops

  • VI of waiting (simulated time)

  • Loop timer Express VI

  • Number of cycles Express VI

  • FIFO, except DMA FIFO

  • Wait on Occurrence with Timeout based on ticks

  • Interrupt the VI, during her wait until this that clear is TRUE

Tags: NI Hardware

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