To access the symbols parolees disable FPGA of host machine

Hello

Is there a way to programmatically access the conditional FPGA disable the host machine symbols? I would like to have a host VI who could know if, for example, the bitfile FPGA has been compiled with ENABLE_AO or not.

solarsd wrote:

Thanks for the tip. I was about to resort to something like that, but I thought that it would be uneconomic in terms of FPGA resources, I didn't know that it was minimal. Furthermore, you happen to know more in detail how something as in the pobrepablo1 example (btw, thanks for the illustration) would be completed in the material? What is the cost of a Panel control before FPGA? I was getting the impression that this is important - in one case, I could only include the VI my FPGA by changing some controls in the constants.

You can get an idea of the use of the resources of statistical resources on the use of FPGAS screws. For example, I chose an FPGA random ones listed, and the table indicates that a Boolean or indicator control uses 3 flip-flops and 3 lookup tables, which is almost nothing. A constant uses resources from 0 (no logic). If your conditional constant disable can have more than 2 values, an 8-bit value is not much more expensive. If you have more than 256 possible values for a conditional disable, you're probably something wrong of course, I would not recommend using a string as in the example of pobrepablo, because it would be very expensive. That's as much detail as I can provide.

solarsd wrote:

I find such behavior of weird symbol be honest. I realize that these symbols are gone after compiling, but everything is managed in a LabView project, if the symbols must be available throughout. I think changing the symbol value will trigger a recompilation of bitfile FPGA anyway, so the 'source' and the binary files are synchronized. The FPGA "bitfile", as I see it, must have a code of host interacting with the driver card hardware FPGA, i.e. where the State of these symbols must be exposed to the user in my opinion. Just trying to understand the logic behind this.

You can configure LabVIEW to open a bitfile on FPGA directly, without the VI used to compile. In this situation the VI and bitfile are not synchronized, and the bitfile could have been gathered in a different project with a completely different set of symbols parolees disable. The only way to guarantee that the bitfile is compiled with the right settings is an indicator on the front panel. You can take a look at the bitfile, it is just XML, and it doesn't even include the version of LabVIEW, used for the compilation. You can use a bitfile to a version with one crowd on the other, as long as the bitfile format has not changed. Disable conditional symbols are removed before the VI (in the intermediate form) is given in the Xilinx tools that actually create the bitfile. NEITHER could add more information, such as the value of the disable conditional, to the bitfile XML symbols, but there should be enough demand for them to do and they would then also need to add a mechanism to access this information. I could be wrong, but I don't know that enough people would find useful to a value of this change, when it is so easy to add an element of façade. Still, you could post on the Exchange of ideas FPGA and see if there is interest.

Tags: NI Software

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