Waveforms digital output duty cycle glitches

I try to use a square wave converted to digital output to operate some solenoids but seeing some problems with the cycle on the digital waveforms. The output frequency will always be of the order of 1 Hz and duty cycle must be adjustable to integer values. I have attached a simplified below, demonstration that shows the digital/analogue output VI I used initially. the problem with this VI, is that if I choose a cycle that is not a multiple integer of my samples for waveform I get seeds. If I use the Boolean digital VI table this problem disappears in my simplified code, but in my real program the problem reappears.

This image shows the waveform analog generated as well as the digital output that results.

In the digital waveforms, you can see that the duty cycle of 50% is sometimes applied during the single loop (~.2us) instead of more than 1 sec iteration, although the curve of actual load indicated in the table at the bottom seems to suggest that LV ignores this glitch (somehow). As I said, the problem disappears if the duty cycle is an integer multiple of the sample/loop. Timing of the loop is torn apart by other e/s to 2 000 Hz/400 samples per loop and 100 Hz/20 samples per loop (large enough VI otherwise I would include it). Obviously, I could change them to get 50% as a multiple, but this does not solve the problem if user needs to adjust from there.

Can someone point me in the right direction here? I'm sure that there is a stupid/easy solution, but I can't seem to get.

Thank you!

You might try turning the inputs A and B of waveform of the VI of the digital samples append.  It seems that A should be the fate of the shift register data (the original data) and B should be added (the new waveform) data anyway, at least conceptually.

Paul P.

Engineering applications

Tags: NI Software

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