When and how does the 40 M Reset counter free running?

Hello friends of LabView,

I use a cRio 9002 controller RT with a chassis of FPGA 9101 and programming for the target FPGA VI.

Now, I would like to know the following:

-What format is the free tick counter 40 MHz running? What maximum ist possible to count?

-What happens if the maximum number is reached? It resets? How long does take?

-Or it just starts beginning with 0 without any time to reset?

Thank you

Marco

Hello Marco,.

using the screws of synchronization for FPGA, you can set the size of the counter internal 8-bit, 16-bit or 32-bit. This size value also sets the maximum possible number, which is the maximum value that can be represented by this record.

There is no setting for this internal counter and he needs no extra time, as noted in LV for 'Number of cycles' help: a free course counter rolls when the counter reaches the maximum value of the internal meter size specified in the configuration dialog box.

I hope that answers your question.

Best regards

Blase

Tags: NI Hardware

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