While the loop within a box Structure runs only once a target FPGA

I have a card OR cRIO-9012 RIO for the HIL system. I have a target FPGA file when I use a While loop within a while loop I use the box Structure to check a real condition inside I have the function of activation of the ports and selecting the analog and digital ports. But for my code the code runs only once on repeted times that we have in the LabVIEW environment.

I also need help to optimize the code. I've seen people using While loop timed in the FPGA target I don't use in both cases.

I've attached my FPGA with the Version of LV2012 file.

Waiting for your comments.

Thank you and best regards,

Ganesha Moorthy

You have while loops inside the structure to deal with a constant of false cable to the stop condition. These loops will obviously never stop so browse your outside while loop (containing the case structure) can never.

This has nothing to do with the FPGA target, the same thing will happen in the development environment.

Tags: NI Software

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