DATA bits of readings of ADS1675 through DIO problems on sbRIO9602 (SPI bus)

Hello

I'm reading THE pieces of TI ADS1675 ADC through interface SPI DATA.

I interfaced 'DATA OUT', "SCLK" and "DATA READY" on 3 entries different from sbRIO DIO on p4 connector.

I built a SCTL @ 40 Mhz state machine to build a basic SPI read protocol on FPGA, but I do not see 24 data bits on the ADC despite the fact that they are there because I checked their presence with the oscilloscope.

SCLK out of the ADC is 8 Mhz so each bit is 125ns wide and change on each SCLK rising on board.

My state machine consists of these States:

  1. Search for DREADY HIGH pass
  2. read DOUT and increments the index where I add then bitten on the next iteration
  3. Search for SCLK rising EDGE
  4. wait for 1 cycle

Basically, I do this:

After a STRONG DRDY is detected I am looking for SCLK rising EDGE (3) and if found, I wait 1 cycle SCTL (4) and (2) 1-bit playback.

This 24 times.

I have TABLE indicator in State 2 where I also updated when I read 1 little...

bit-wise or rising-falling edge is about 3ns so I guess that wait 1cycle after SCLK rising edge detection is enough to read a stabilized value of corresponding DATA OUT bit... but I just kinda of 24 elements of array flashing but no correspondence between Word detected thanks to an oscilloscope and TABLE on the front...

Do you have a suggestion or SCTL SPI examples?

Thanks iin advance

OK I found the bug... just I haven't set the table of Boolean on a register to lag on SCTL so I've been updating and lose sistematically every bit that I was updating the table...

now I can see the correspondence between the bits of data shown on the oscilloscope and the table of Boolean

Tags: NI Hardware

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