Distribution of LVOOP/FPGA-based application on several possible projects?

SITUATION: I develop a large enough project that relies heavily on LVOOP: I encapsulated material-interaction and functionality in the classes of LV that are loaded at run time. I have different types of plug-ins that are interacting with each other in the first level VI. These types of plug-ins are made in more generic classes defining their interfaces that are used by the top-level VI. Plug-ins actual instantiated at runtime classes are child-classes of matching the more generic classes (dynamic distribution).

PROBLEM: The Labview project file is now big enough and takes forever to load/save. Also, I regularly get crashes or other very odd behavior of Labview himself. For example, Labview stalls when loading the project file, except when it is loaded through the list 'recentlly open project' in the start menu in Labview.

POSSIBLE SOLUTION: I would like to make an individual Labview project file for each plugin real. This would have the additional advantage that they could be indivually developed by different developers without cause version conflicts.

The PROBLEM WITH THIS SOLUTION: First tests show that it would work in effect plug-ins that do not target FPGA use. However, many of my plug-ins use the FPGA screws, which are still features some plug-ins (i.e., some plug-ins can use an FPGA VI, while others use it an another VI FPGA: a single FPGA VI will run both, however). For this reason, I would like to put these FPGA VIs in Labview for the plug-in project only, but not in the top-level Labview project. Because otherwise, I would have to update the project level higher every time that someone has written/edited a plug-in that uses an FPGA VI.

Unfortunately, Labview generates an error when executing in the first level VI a method of a class of plug-in that uses an FPGA VI: "1498 error in Get LV class by default Value.vi. Possible reasons: LabVIEW: library has errors. Correct the errors before performing this operation. "Complete the call chain: get LV class default Value.vi top_level_vi.vi.

In fact, it not even help to add to the project LV level the target FPGA including the FPGA VI which will be called: the error message remains the same.

QUESTIONS RELATING TO THE:

-Is it possible to distribute the LV classes on various projects with some of these projects with their own VI FPGA/resources dedicated.

- Or is there a completely different solution to avoid a huge project file LV with problems?

Thanks in advance for any help!

I discovered that you can access an FPGA VI without adding all resources FPGA (for example the FIFOs, i/o etc.) for the respective project by obtaining the FPGA VI reference via bitfile VI (unlike obtaining by the path of the VI). Exactly what I needed. I now have a project containing the FPGA resources and live FPGA. And in all the other projects that I can make use of the FPGA screws without adding resources FPGA, just by opening the bitfile FPGA VI related references.

The idea of encapsulating the FPGA VI in own LabVIEW class is also very useful. In combination with obtaining the FPGA VI reference via the bitfile it allows me to charge flexibly different screw FPGA running (according to the settings in the configuration files), again without having to add any combination of FPGA resources to the project.

Problem solved. Thank you!

Tags: NI Software

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