FPGA Express PID vs Custom PID behaves differently? Whats is wrong

Hi all

I try to use labview FPGA Express VI in my application with cRIO 9022. I write a custom PID and compare the result with the FPGA palette express PID.

It seems that the integral action on the express PID is too large.

I am using PID as a simple Integrator providing zero gain proportional and derivative and Ki = 1. Which provides a signal error of 0.1 and sampling time of 1/5000, after 10 sec, the Integrator must accumulate 1. As usual, we he reach apprx. 10 sec, the express VI increases quickly until saturation.

What is the problem with my VI, I'm sure I'm missing something. The reason why I want to express is that it consumes less space and I have to use 5 parallel PID which I just can't get with a custom because it is written not effectively. I attached the VI and the png for your view.

Thank you all,.

Some.

Well, the ZIP file is valid, but I'm on an older version of LabVIEW, so I can not even open your screws, sorry.

I would check your math. Aid for the VI Express FPGA is clear on the functioning of the calculation. It does not count the sample time - which is one of the reasons that gains are standard. Configured the way you need your code, the error integrated - and therefore the output - increase 0.1 for each iteration of the loop, regardless of the rate of loop - so it will take 100 iterations for output reach 10. You can set your full winnings to take account of the actual loop cycle time.

Tags: NI Software

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