Question of scaling of the FPGA 2009 PID.vi LV

Similar Questions

• How can I get the Coefficients of scaling for the Butterworth filter FPGA version

  I am trying to program a FPGA application where I need to be able to change the cutoff frequency of the filter.  I see that I can do a terminal for the coefficients of the filter on the VI express Butterworth filter, but how to generate the coefficients of different cut-off frequencies of filter?  When I use the VI of Coefficients of Butterworth host-side small floating-point values rather than the large fixed point values I see on the side turns FPGAS.

  Thank you

  David R. Asher

  Hi David,

  8.5 or 8.6, there is an example of navigation that contains the Subvi design filter you need:

  examples\R Series\FPGA Fundamentals\Analysis and Control\Filter and filter Butterworth Reconfigurable DC-RMS\Using-R - series.lvproj

  In LabVIEW 2009, there is a new palette in my computer: Interface FPGA > scaling, with a new VI of Coefficients of Butterworth on this subject. Who will produce the coefficients quantified, you need in the format expected by the FPGA Butterworth filter.

  Kind regards

  Jim

• How many modules NI 9505 can I program the FPGA (with SoftMotion) NI 9104?

  Hello.This is my first question here. When I try to make the FPGA code to four NI 9505 (with loop position (including SplineEngine), current loop, loop PWM and encoder loop) I simply double code for module four times. I use the NI 9104 chassis with 3 m doors, but compiler returns compilation error (I guess, code does not fit on FPGA). I tried to make the code more simple (I combined some terminals). But it did not help me. Thanks to lot.P.S. sorry for my English.

  This message may be a bit delayed - but I did a lot of work to obtain many 9505 modules compiled on a number of different FPGA targets. Seven on a Virtex-II 3 m gate FPGA and eight on a 2 million doors Spartan3 (don't be fooled by the size of the door - the Spartan FPGA tends to be more effective in the compilation of size, but the worst with a timing compared to the Virtex II. The Virtex5 are better all around).

  They key is "mulitplex" code - in particular the SoftMotion contructeurs algorithm. Multiplex in this sense means both use the same code for each axis and process things in series parallel vs. Because the constructor requires the backup of important data for each axis between the loop itterations, use of these VI block of RAM on the FPGA vs using large arrays in FPGA fabric.

  I have attached a code that will work with LabVIEW 8.6 and SoftMotion 2.2. This will NOT work with 2009 SoftMotion (RT both the FPGA VI changed).

• The Sierra of MacOS will propose for the Mid 2009 MacBook Pro in the near future?

  I have a model Mid 2009 MacBook Pro and when I try to upgrade the software of OS systems to the Sierra, he refused my request to download because it "cannot be downloaded to this computer." I noticed other Mac computers, for example, iMac Mid 2009 or newer and MacBook Mid 2009 or more recent systems only one are close to mine are candidates to download the software, but the MacBook Pro is the only one that is not on this list for availability. So, my question to my question is, will be available Mid 2009 MacBook Pro updated to day for Sierra anytime soon? And if not, why?

  Please let me know what your answer is as soon as possible.

  Thank you!

  My answer is no.

  However, as long as I and everyone here, do not work for Apple, my answer is certainly not authoritative.

  However, as I've used Apple computers for more than 30 years, he never had a case when they released an additional OS that works on previously excluded material.

• Safari with question marks instead of the text

  Several Web sites in Safari 9.1 showing many points of question marks instead of the text. I just proposed by Apple and done nothing. I have Imac (late 2009) OS X El Capitan 10.11.4.

  Question marks instead of the text is an indication of a problem with fonts.

  Open the book fonts in your Applications folder.

  In the fonts start menu bar click book fonts > Preferences and then click: resolve duplicates by moving the files to the trash

  Quit and then restart Safari to test.

  If this does not help, back to the font book menu bar click file > restore to the Unicode Standard

  Quit and then restart Safari to test.

• Broken the FPGA VI but the empty error list

  Hello!

  I'm trying to run a vi which includes a 'Open FPGA VI Référence' function. However, an error and it says that "not compiled FPGA VI. When I try to compile the FPGA VI a message saying "The VI is broken". I try to run the FPGA and when appears in the error list, there is no error or warning in the list, although the name on the fpga includes the Red 'X' ('show warnings' is checked). Any help?

  I'm using Labview 2013.

  Pablo

  Hi Pablo.

  Sorry for my delay in responding, you managed to get the respected FPGA.vi yet?

  To answer your questions, if the project is ok with an empty FPGA.vi, then in theory, your hardware is configured ok. However, due to the vi being blank, you haven't tried to use one of the modules on your system, so it can introduce errors. The most common mistake is differentiation of mode Scan Mode/FPGA by installing the project in the first place. Also be aware that not all FPGA targets supports everything, for example some dislike for the rows that have an index to calculate the number of iterations, rather than a constant wired at the entrance to "n".

  Out of curiosity, why you place every measure in the DMA separately and also specify address? Is there a reason you don't just place all the measures in a table and put everything in the DMA, then divide the table on the other side?

  Generally speaking I don't think that incorrect programming should never cause LabVIEW crashing and you should always report the problem to the OR in order to take a look and see if they can fix it.

  Hope that you managed to get your problem sorted and again sorry for the late reply.

  Darren.

• FPGA Express PID vs Custom PID behaves differently? Whats is wrong

  Hi all

  I try to use labview FPGA Express VI in my application with cRIO 9022. I write a custom PID and compare the result with the FPGA palette express PID.

  It seems that the integral action on the express PID is too large.

  I am using PID as a simple Integrator providing zero gain proportional and derivative and Ki = 1. Which provides a signal error of 0.1 and sampling time of 1/5000, after 10 sec, the Integrator must accumulate 1. As usual, we he reach apprx. 10 sec, the express VI increases quickly until saturation.

  What is the problem with my VI, I'm sure I'm missing something. The reason why I want to express is that it consumes less space and I have to use 5 parallel PID which I just can't get with a custom because it is written not effectively. I attached the VI and the png for your view.

  Thank you all,.

  Some.

  Well, the ZIP file is valid, but I'm on an older version of LabVIEW, so I can not even open your screws, sorry.

  I would check your math. Aid for the VI Express FPGA is clear on the functioning of the calculation. It does not count the sample time - which is one of the reasons that gains are standard. Configured the way you need your code, the error integrated - and therefore the output - increase 0.1 for each iteration of the loop, regardless of the rate of loop - so it will take 100 iterations for output reach 10. You can set your full winnings to take account of the actual loop cycle time.

• Synchronize the FPGA clock for clock RT?

  Hello

  I use a sbRIO-9612.  Data are acquired for several weeks, and the problem is that the clock of RT of derivatives. I found a technical document to synchronize the clock of RT with SNTP server:

  http://digital.NI.com/public.nsf/allkb/F2B057C72B537EA2862572D100646D43?OpenDocument

  But I do not find anything on the FPGA clock. My data are acquired by the FPGA, my question is: How can I synchronize my FPGA clock with my RT clock or the SNTP server? (this is probably a stupid question, but she clearly explains my problem) SbRIO is suitable for my needs? Should I waive any 'acquisition of FPGA based' and use a different hardware architecture to perform data acquisition synchronization?

  Thanks in advance for any help.

  Julien

  Hi Julien,

  Take a look at "RT masters FPGA synchronization Example.vi" on the FPGA Timekeeperpage.  There's a Subvi, which uses a timed writing periodically present to the FPGA so that the FPGA can have a domain time synchronized with respect to RT if you have questions about this example, try to publish to category of Discussion of the project.

  -Steve K

• Number of DMA FIFO of items to read mismatch in the FPGA and RT

  Hi all

  I use myRIO, LV14 to run my application.

  Request: I have to continuously acquire data via FPGA and host RT process once every 2000 samples are taken. I use DMA FIFO (size 8191) to acquire data, use timeout property in the FPGA to eliminate the buffer overflow. I had followed cRIOdevguide to implement this part. An excerpt of what I put in place is attached. All code runs in the SCTL at 50 MHz.

  Question: Two or three times I met with this strange behavior, the FPGA FIFO gives continous timeout and the RT is unable to read the FIFO. The number of elements to set the property in the FPGA VI gives 0 showing that FIFO is full and no more can be written, but the RT, remaining items gives 0, so it is reading 0 (none) elements.

  Solution: I put a case where I'll write to FIFO (under the code) and if the number of elements to write is different from zero. It seems to work fine, from now.

  What confuses me, is that my FPGA VI said that FIFO is full (number of items to write 0 = FIFO) and gives a timeout error, but RT VI said that number of items remaining in the FIFO is 0 and therefore no data is read. No idea why this is so? My RT and FPGA VIs continues to run, but with no gains or to read data.

  A few minutes after you run the code, I've seen this behavior. No idea why this happens? I try to reproduce the behavior, and will update if I meet with her again. Sorry, I can't post my code here, but I guess the code snippets to explain some extend.

  Thank you

  Arya

  Edit: Even with the mentioned workaround solution, the problem persists, now that the FPGA written any of FIFO. And the RT VI is not able to read all the elements he sees 0 items in the FIFO. The FIFO continues to be in a State of timeout. So I guess that the problem is on the side of RT.

  Why it looks like you read from the FIFO even in two different places in the same VI, at the same time? If the lower reading throws the FIFO, it will never trigger the reset, which could lead to the situation you describe, I think (it's hard to tell from a few screenshots).

  Also, your logic seems too complicated. I immediately noticed that there is no reason to select the entry, the output of = 0 - simply use the 'equal to zero' output directly. On the side of FPGA, why you need check the number of items that you want to write? There's nothing wrong with writing in a FIFO that is already full. just the data won't get written.

• Spartan - 3 driver and Labview FPGA 2009

  Hello

  Do we need a new Spartan-3E driver to work with Labview FPGA 2009? And, if so, is it provided by National Instruments?

  Thank you

  Walid F. van

  Hello everyone

  The driver for the Spartan 3rd WHAT XUP Starter Kit are now on the site OR here:

  http://digital.NI.com/express.nsf/bycode/Spartan3E?OpenDocument&lang=en&node=seminar_US

  Just click on the link to get driver.

  Kind regards

  John Harvey

• Impossible to check the FPGA reference with "not a number/path/Refnum?

  How can I check if an FPGA interface refnum is valid?  It seems (LabVIEW 2009) that "Not a number/path/Refnum?" always returns true when connected to the output of open FPGA VI reference.  I write code that needs to be able to run without an FPGA for testing purposes, so I wrapped all calls to the FPGA in a case structure that I thought would run only if the FPGA reference is valid.  Turns out that they run ever, even when the FPGA reference is valid (probe shows it has a numerical value, and the FPGA VI is running).  I guess it's sort of similar to semaphore and appointment of references that have their own special function to verify the validity, but I do not see such a function for FPGA.  I have to cast to int and check if it is not equal to zero?

  
  

• Effective use of the FPGA read/write

  I am writing an application for a CompactRIO real-time and I am looking for ways to simplify my code and reduce the CPU usage. I use FPGA to do much CAN e-mail and signal processing, then I have a VI running on the real-time processor that reads values in the FPGA, does some processing and outputs data in the FPGA. My code running on real-time parallel uses several loops running in a master/slave architecture. A single loop reads all necessary information in the FPGA in indicators and writes the values of the controls in the FPGA. The other loops read entries and manipulate the outputs via local variables.

  My question if it would be more effective to get rid of the loop which is dedicated to the communication of FPGA and has of each loop to read and write directly on the FPGA. If I use a reference block FPGA open and use the reference of the output in several loops, each read/write operation block others until it's over? Each output is changed only in one place in the code, but there are several entries that are used by multiple loops. It is even more effective for each loop of read/write for the FPGA on request? How will this affect determinism?

  Thank you

  Jon

  Jon,

  Read/write controls is not deterministic, but I think that your previous method should work just fine, as long as you have that unique writers. If you have multiple writers, you start affected by race conditions.

  I don't think you will see a significant improvement in the performance/CPU in the alternative method. You would see big performance gains if your master loop reads more slowly indeed, but it's always a compromise.

• No option of scaling on the atom z2760

  First of all, some of the statements.

  (1) I bought new Acer W510 recenltly tablet.

  (2) I'm big fan of old games and I am buying on gog.com

  (3) I can't play old fashion games full screen due to no option scaling on the z2760 Atom graphics!

  (4) Intel web site says they have no dedicated driver for Atom z2760 and that I should ask my camera manufacturer.
  

  ( http://www.intel.com/support/graphics/sb/CS-033838.htm)

  (5) you can't play games that have no support for the resolution of 1366 x 768, since they reduce right in the center of the screen of my W510 and evrything is really small.

  Question
  

  Is there a way that acer would update graphic driver for Acer w510?
  

  Thanks in advance.

  Now, first of all check list update game to win 8.

  http://www.Joystiq.com/2012/11/26/Gog-adds-Windows-8-support-431-Games-compatible/

  And report the problem to the request to support on the z2760 atom.

  However application to support it soon.

• I want to reset my security questions, but there not the possibility of

  I want to reset my security questions, but there not the possibility of

  Click here > If you forgot your Apple ID - Apple Support security questions answered

• How can get answers to the question of security of the apple account

  How can I get answers to my account security question?

  See the following link for instructions: If you forgot your Apple ID - Apple Support security questions answered