FPGA IO node and loop Question of Timing

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  What I said OR the 'Start asynchronous call' is the preferred method for starting background tasks. This call is usually used to run background tasks. For example, you have a process of journal. When your application starts it would use the "asynchronous call Start" to start the process of journal and then move on to the other stuf. The process of the journal would then happily run in the background and the main application is free to do other things. Of course when implementing these types of systems you need a way to coordinate things like exit. This is where the queues and stuff come it.

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  I'm having some difficulties to understand how the clock is part of the node IP for LabVIEW FPGA and was hoping to get some advice.

  What I try to do is to set up a digital logic circuit with a MUX feeding a parallel 8-bit shift register. I created the schema for this Xilinx ISE 12.4, put in place and can't seem to import the HDL code into an intellectual property node. When I run the VI, I am able to choose between the two entries for the MUX, load the output in the shift register, clearly the shift register and activate the CE.

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  -Specify the CE in the process Configuration of the IP nodes.

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  -Various reconfigurations of the same thing that I don't remember.

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  I spoke to the engineer OR this topic and it seems that it was sufficient to verify that your code works, by putting a wait function of 500 ms on the while loop to check that the registers responsible and clear. I'm glad that it worked very well!

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  Post edited by: Umair_ali

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