Using of FPGA VHDL IP and analog output

I use a system with Labview 2014 PXI. I've got Labview FPGA to program and run the card PXI-7854R.

I have the VHDL Code I want to use to control an analog output of the card. I use the IP integration node for this now but I also tried it making the process CLIP and still have not been successful. The problem that arises is that the IP integration node must be in a timed loop, while the analog output indicates that it cannot be put in a timed loop. Is there a way to provide an output of VHDL analog outputs of the card?

I tried to embed a loop timed within a while loop, but it still does not work.

I can't download the VI due to the policy of the company, but suppose I'm generating a sine wave in my VHDL code which must lead to the analog output of the card (the actual wave is company owner information but it is generated by a glance to the top of the table as a sine wave VHDL would be).

In an attempt to work the problem I retried import CLIP of the HDL code in a new project in Labview and VI. I'm still not sure about why it did not work with each other when I tried it.

For anyone who seeks to solve this problem:

I basically used this tutorial for the process CLIP: http://www.ni.com/tutorial/7444/en/

It also explains the differences between the CLAMP and the IP integration node.

Tags: NI Software

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