FPGA programming depends on the time

I think my problem is simple, but I need help...

In an FPGA VI, I acquire an entry and compare it to a control (if the input is greater than the order, the contiues code with an error response).

What I want to do is to add a condition of time.

I want to continue only with the error response if the entry is greater than the order and she was superior to the command for x amount of time.

What is a good way to do this?

Thank you.

I adapted the code for the example of watchdog of 2013 below. Rather than wait for the watchdog to kill himself, he expects the IO above the threshold of safety. It is set in milliseconds, but you could use ticks of better resolution, just make sure to keep your loop in mind.

You can see an example of the documentation on the code works if you need

Tags: NI Software

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