How to increase the level of Effort BY?

Hello

I am trying to restore a primary application of a number of separate projects of component LVFPGA LVFPGA.  Each of these smaller basic functions is running in their own SCTL in new the LVFPGA master file.  Small functions all meet them timing, but not the master app.

I use about half of the chip so it seems to me that it should not be difficult to place and route.

When my compilation fails because of time constraints, he says the following:

WARNING: By: 62 - your design did not meet calendar.  Here are some suggestions to help you to keep to the timetable in your design.

...

Increase the setting of the level of Effort BY to 'high '.

Use the 'xplorer' Xilinx script to try special combinations of options known to produce very good results.

See http://www.xilinx.com/ise/implementation/Xplorer.htm for more details.

So my questions are:

(1) how can I increase the level of Effort BY?  Has NEITHER provided a hook for setting this value and if so what is its current level / by default?

(2) we access level user to the script 'xplorer '?  If so, where is this located and can OR recommend some parameters that are compatible with the SMU-5641R.

Thank you

The files in the folder of Xilinx are never overwritten or replaced, these default values are simply not used if you provide your own .opt files to the compilation sequence. For these two products, we provide custom files, I've already mentioned. These custom options are communicated to the server during each request compilation as it must have everything necessary to provide correct results regardless of compilation locally or remotely (or even on a remote compiling the server who has not installed the drivers from target).

Insofar as you need exactly what settings level effort, which will be dependent on the design. I suggest you look at Xilinx documentation on their suggestions on how to set these options based on what kind of compile questions that you hit. In general, I would try them likely increases in the following (probably with compilation time) order:

"" plan of access-Calendar - ol std' and ' normal - ol std ".

'map - calendar - ol high' and ' "normal - ol std".

"map - calendar - ol high' and ' by - ol high."

[Or if you will just operate all night and don't care about compile time, you could jump to top/high... and work backwards if you want to use the minimum effort it takes actually.]

If these don't work for you (or if you want an alternative solution), then you need to review your design and your code to see if you can improve the synchronization in the areas which are at the origin of chess.

Side-note:

Modifying the files in the directory of Xilinx does not apply to this situation. I do not know the behavior to change these files, but it would be easy to deduce by experimentation (i.e. edit the file locally, perform a remote generation, see if the changed options were used... If not, then restore the local file, the remote file instead, rebuild, etc.). But even once, it does not apply to these objectives and behavior will be verified based on file by a specific version of LabVIEW file, since it is an implementation detail that may change.

Tags: NI Products

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