Similar Questions

• How to import codes Verilog in LabVIEW FPGA?

  I tried to import the Verilog code by instantiating followed education in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3.

  but I can still see some errors when compiling the file VI.

  Test file simple Verilog is as follows:

  ==============================

  module andtwobits (xx, yy and zz);

  input xx, yy;
  output reg zz;

  always start @(xx,yy)
  ZZ<= xx="" &="">
  end
  endmodule

  ==============================

  and after you follow the above link, we have created the instantiation as file

  ==============================================

  Library ieee;
  use ieee.std_logic_1164.all;

  mainVHDL of the entity is
  port)
  xxin: in std_logic_vector;
  yyin: in std_logic_vector;
  zzout: out std_logic_vector
  );
  end mainVHDL;

  architecture mainVHDL1 of mainVHDL is

  COMPONENT andtwobits PORT)
  ZZ: out std_logic_vector;
  XX: in std_logic_vector;
  YY: in std_logic_vector);
  END COMPONENT;

  Start

  ALU: andtwobits port map)
  ZZ-online zzout,
  XX-online xxin,
  YY-online yyin);

  end mainVHDL1;

  ==============================================

  Sometimes, we observe the following error when we put the flag on the output port.

  ERROR: ConstraintSystem:58 - constraint

  TNM_ChinchIrq_IpIrq_ms; > [Puma20Top.ucf (890)]: INST
  "* ChinchLvFpgaIrq * bIpIrq_ms *" does not correspond to design objects.
  ERROR: ConstraintSystem:58 - constraint
  TNM_ChinchIrq_IpIrq; > [Puma20Top.ucf (891)]: INST ' * ChinchLvFpgaIrq * bIpIrq. "
  does not match design objects.

  and Interestingly, if we remove the indicator from the port of exit, he sucessfully compile on the LabVIEW FPGA.

  Could you take a look at and please help me import Verilog to LabVIEW FPGA?

  I followed the basic steps of the instantiation on the link above, but still it will not work.

  Please find the attachment for all files.

  -andtwobits.v: original file from Verilog

  -andtwobits.ngc: file UCS

  -andtwobits.vhd: VHD file after translating a simulation model

  -mainVHDL.vhd: master of the instantiation

  Since there is no sample file for Verilog (VHDL file, there but not for Verilog), it's a little difficult to do simple execution on LabVIEW FPGA, even for examples.

  Thank you very much for your support, and I'm looking forward to seeing all your help/answer as soon as possible.

  Records,

  The best instructions we have for integration Verilog IP in LabVIEW FPGA can be found here: using the Verilog Modules in a component-level design. My suspicion is that you did not uncheck the option 'add the IO buffers' in the Xilinx ISE-specific Options parameter when running XST (see page 8 of the .pdf)

• Use of user defined function in mathscript containing a structure

  Hi, I am a novice user of LabView MathScript module,

  I have the following problem when integrating my code MATLAB, LabView, for HMM: in my program, I tried to call a MATLAB called "mixgaussinit.m" user-defined function, it shows this error...

  "

  I just noticed that these files appear to be copyrighted. My first question is do you have author permissions to post them in a public forum? If this isn't the case, then you can remove them. That being said, I have reviewed the code and it seems easy enough to work around your problems (provided that you have the copyright permissions). How to bypass the problems is to replace the fields of the struct with variables. There is of course allows you to change some definitions of functions for input and output the necessary variables which I think was the best 5 variables. You will also need to redo the code that uses a table of error checking cell. In total, I estimated about 30 minutes of work. I would have given you work around these files had not been protected by copyright. So, unfortunately, you will need to implement the work around you.

• How to load a pointer data memory in table

  I'm trying to interface to a DLL used to manage a piece of hardware. The DLL is written in c. uses _stdcall and the Import Wizard has hooked up with success of most screws in a library; many of them work everything just as it is. I have also played with the knot of library function call and think that most of the time, I got the hang of it. I ran successfully for the odd Windows API call (e.g., MessageBox). However, I am a newcomer in Labview. My problem is related to a DLL function that requires a pointer to a block of memory, in which he then dealt with the material (in the form of table of UINTs) data. I want to display these data in Labview, through a table I guess. I think I found everything I need to do in terms of creating a table and hanging until the node of library function call with an input pointer.

  I hope this would work IF the block of memory has been fully completed until the function has returned. HOWEVER, this is not how the DLL function. It creates a thread that exert to put data in the memory block after the function in the DLL. Extra features are available for face to discover if the data transfer is complete. I guess this is enough to refute the marshaling of data in Labview, unless there is some special commands for this purpose.

  I thought maybe I should allocate the memory using the Windows API (LocalAlloc LPTR flagged so I get a pointer) and I wrote a little VI that allocates and releases the memory that seems to work. This way I can release memory when the transfer is complete. MY PROBLEM is, given the pointer to the block of memory, as returned by LocallAlloc, how can I get Labview to read the memory in an array of integers.

  I am now a little stuck and would like to receive advice on one, how to convert the block of memory, or on a way to approach things btter.

  TIA

  SteveJM wrote:

  So I have a working solution, which is basically the same idea as your suggestion, but uses the Windows API. I took the trouble to mention it, but when I looked more closely at 'MoveBlock', 'DSNewPtrt' etc, I realized that they are a static C library. This means that using them requires that you have a C development system and knowledge how to build DLLs on that. As it happens that causes me a problem, but it seemed like a hammer in this case because the routines you need are already in the kernel32.dll module. [Yes that makes specific Windows, but then you would need rebuild your dll for each operating system in any case].

  This paragraph is completely inaccurate.  These functions are integrated into the runtime LabVIEW, without which your LabVIEW code will not work.  You have the guarantee that if you can run your LabVIEW code, or in the development environment or as a compiled application, these functions are available.  No need for a C development system (if that were the case, don't you think someone would have mentioned in one of the many messages on this forum on the use of MoveBlock?).

  SteveJM wrote:

  It is true that you need to find a way to pass the pointer to the destination of reference. In other words, using a "handful" I guess. One of the difficulties is that the documentation for Labview is rather imprecise on what happening coming in and out of the function call. Unfortunately, the meaning of "Handle" is very dependent on context, so documentation should be much more detailed. If you select 'Manage' rather than "Pointer table" minimum size box disappears implying that Labview will take a pointer to a pointer to a format of Labview. It would then allow the size information in the allocation of the table and set the offset pointer approprately when passing a pointer to the function that would fill the memory. If the size of the table was large enough, it might be useful to tweak with this to avoid the copy useless (and allocation), but I don't have time now, unless I find the best literature which explicitly explains this gathering takes place for each option in the dialog box.

  All the help you need is available.  Set up a call library function node to pass by handle, close the configuration dialog box, right-click on the function call library node and choose Create .c file...  You will get a draft of C with all structs defined for you, and you will see that the handful of LabVIEW table includes size information.  There is no "triage."  He is just passing pointers autour (and a few and Word-permutation of bytes due to problems of "endianness").  When you pass an array of pointer to array value, you get what you expect - LabVIEW dereferences the handle once and passes the pointer of table.  It's exactly like a C function call.  Nothing unusual occurs when the call is returned (with the exception, even once, "endianness" switch if necessary).  That said, it's a bad idea to do what you want to do with a handle, because LabVIEW is allowed to move the table when he likes and has no way to know that some other functions still has this memory block to stay where he is.

• Frequency-wave number domain

  I would like to turn my non-stationary ground penetration radar and the seismic signals from the time domain to the frequency-wave number domain in my LabVIEW 7.1. The goal is that later f-k/Stolt migration. But I have found no useful VI in LabVIEW. Y at - it all?

  Thank you.

  Wallace

  Greetings Wallace.

  Unfortunately, to my knowledge there is no integrated inherent method of LabVIEW to perform this operation.  While we have another screw for the conversion of area, such as the field of simple time in the frequency domain, etc., this seems to be outside the scope of what the development system and tool boxes offer at present.  If you think it would be a good feature to include in LabVIEW, please feel free to create a product suggestion to www.ni.com/ideas.

  Kind regards

  Michael G

• color change of tank when the entry of a simulink crosses the threshold

  Hi all

  I want to change the color of the indicator of tank in labview from green to red when the input in simulink signal crosses a threshold. In fact I'm integrating simulink and a labview using connection OR SIT.

  Thank you

  Muhammad Abul Hasan

  
  

• does anyone have a good recommendation for a voltmeter of PoE that can be integrated into Labview/TestStand?

  I started looking for a voltmeter of PoE, but so far all the ones I've found are for use of the mobile hand held.   I'm looking for a version that can be integrated in an automated production environment.

  Can someone point me to a voltmeter of PoE who has control USB or ethernet.   Ideally with Labview drivers. But if I do these myself I'll be okay with that.

  Unfortunately, I've not seen anything quite like that around. The closest I could find was the PoE3N-reach technology RT, which looks like it might have connectivity RS-232.

  Another option might be to type the tensions of the ESP and read those who use a more general tool as a DMM device or data acquisition. Something like the POET systems-FM-1. Maybe something like this work?

  There may be someone on the forum who is more familiar with POE that I am, but that's what I was able to dig up.

  William R.

  National Instruments

• VSS of LabVIEW integration issue

  Hello

  I'm trying to simulate jointly VSS and Labview by running a simple example of the AWRDE example file. I get the error message that I need license of integration (see the attached screenshot) in order to use the LabVIEW block in VSS. I'm under LabVIEW 2013 Professional Edition and have the next version of AWR:

  10.02R build 5983 Rev (78833). I have Windows 7 on my computer.

  Can someone please tell me what is license integration and how to get it. We have the license for LabVIEW, as well as software AWRDE. Thank you.

  Kind regards

  Kathar

  Hi, Kathar, the best way to fix this is to upgrade to AWRDE v11.01 (available from the download link at www.awrcorp.com).

• How to install the version of nor-Sync 3.1 in the remote system (processor integrated PXI chassis) to recognize the PXI-6682 device to work with labview RT?

  How to install the version of nor-Sync 3.1 in the remote system (processor integrated PXI chassis) to recognize the PXI-6682 device to work with labview RT?

  Hung Nguyen

  Hung Nguyen,

  The installation of drivers for all targets in real-time remotely is more or less the same. First install the driver (in your case the NO-Sync) on your PC, then install it on your system remotely through MAX. For step-by-step instructions, see install the software on your NI CompactRIO controller.

  See you soon,.

• All power back on "LabVIEW: [connected] A Real World integration Developer Guide.

  Any comments on

  "LabVIEW: Guide the developer in the real world integration [connected].
  "  ?

  IMHO, the course of LV connectivity and you know as much as the authors - perhaps more.

  Mike...

• Discreet Integrator (control and Simulation Module) - LabVIEW 2015

  Hey everybody,

  I'm trying to drag the discreet Integrator on a block in 2015 of LabVIEW diagram. All other vi in the "range of discrete linear systems are draggable, but not the"discreet"Integrator." I noticed the same thing for the continuous Linear Systems Integrator. Anyone explain how to solve this problem?

  Sincerely,

  Lex

  Lexicondi,

  Unfortunately, these functions cannot be moved out of the loop control & Simulation. We support only discrete transfer, of State spaces and ZPK models function.

  So, if you want the "discreet Integrator" outside of the SIM card, you have the following options:

  one) to use the "discreet transfer function" as T /(z-1) (or any other type of discretization available in discreet Design continuous monitoring);

  (b) you can develop your functions inside the control and the Simulation loop and then create a subsystem of her. The subsystem can move outside the SIM card also. Here, you can use any SIM function you want;

  I hope that this should be sufficient for your application.

• Integration of IP node evil in LabVIEW FPGA

  Hi all

  I am having trouble with the integration of LabVIEW FPGA IP option and was hoping someone could shed some light here.

  I use a simple VHDL code for a bit, 2: 1 MUX in order to familiarize themselves with the integration of IP for the LabVIEW FPGA.

  In the IP properties of the context node, the syntax checking integration says:

  ERROR: HDLParsers:813 - "C:/NIFPGA/iptemp/ipin482231194540D2B0CC68A8AF0F43AAED/TwoToOneOneBitMux.vhd", line 15. Enumerated value U is absent from the selection.

  but I'm still able to compile. Once the node is made and connected, I get the arrow to run the VI but when I do, I get a build errors in Code Pop up that says:

  The selected object is only supported inside the single-cycle Timed loop.

  Place a single cycle timed loop around the object.

   

  The selected object in question is my IP integration node.

  I add a loop timed to the node, but even if I am able to run the VI, it nothing happens. the output does not illuminate regardless of the configuration.

  I would say that I tried everything, but I can't imagine would be the problem might be at this point given that everything compiles and the code is so simple.

  I have attached the VI both VHDL code. Please let me know if any problems occur following different boards of the FPGA.

  Would be really grateful for the help,

  Yusif Nurizade

  Hey, Yusif,.

  Looks that you enter in the loop timed Cycle and never, leave while the indicator of Output never actually is updated. Try a real constant of wiring to the break of the SCTL condition. Otherwise, you could spend all controls/indicators inside the SCTL and get rid of the outside while loop. You can race in the calendar of meeting bad in larger designs without pipeling or by optimizing the code if you take this approach, however.

• LabVIEW FPGA: Integration node clock wrong

  Hello

  I'm having some difficulties to understand how the clock is part of the node IP for LabVIEW FPGA and was hoping to get some advice.

  What I try to do is to set up a digital logic circuit with a MUX feeding a parallel 8-bit shift register. I created the schema for this Xilinx ISE 12.4, put in place and can't seem to import the HDL code into an intellectual property node. When I run the VI, I am able to choose between the two entries for the MUX, load the output in the shift register, clearly the shift register and activate the CE.

  My problem is that when I switch to the entrance of THIS, he should start 1 sec shift (Boolean true, SCR, High, what-have-you) in the registry once each clock period. Unfortunately, it instantly makes all 8 bits 1 s. I suspect it's a question of clock and here are some of the things I've tried:

  -Specify the input clock while going through the process of configuring IP nodes.

  -Adding an FPGA clock Constant as the timed loop.

  -Remove the timed loop and just specifying the clock input (I'm not able to run the VI that I get an error that calls for a timed loop)

  -Do not specify the clock to enter the Configuration of the IP node and wiring of the FPGA clock Constant to the clock input (I can't because the entry is generated as a Boolean).

  -Remove an earlier version of the EC who had two entries up to a door and at ISE.

  -Specify the CE in the process Configuration of the IP nodes.

  -Not specify this in the process of setting up nodes IP and wiring it sperately.

  -Various reconfigurations of the same thing that I don't remember.

  I think I'm doing something wrong with the clock, and that's the problem I have. Previously, when I asked questions to the Board of Directors on the importation of ISE code in LabVIEW FPGA, a clock signal is not necessary and they advised me to just use a timed loop. Now, I need to use it but am unable to find an explanation online, as it is a node of intellectual property.

  Any advice would be greatly appreciated, I'm working on a project that will require an understanding how to operate clocks the crux of intellectual property.

  Thanks in advance,

  Yusif Nurizade

  P.S. I have attached my schematic ISE and the LabVIEW project with one of the incarnations of the VI. The site allow me to add as an attachment .vhd file, but if it would help I could just paste the body of the code VDHL so just let me know.

  Hello Françoise,.

  I spoke to the engineer OR this topic and it seems that it was sufficient to verify that your code works, by putting a wait function of 500 ms on the while loop to check that the registers responsible and clear. I'm glad that it worked very well!

• LabVIEW created DLL that uses Labview live integrated Toolbox "DFD" (Digital Filter Design)

  We were using a Labview created the DLL file that uses the screws of the DFD Toolbox, but were not able to operate at all. Now, we have replaced the DFD screws with screws that built us, and the DLL file works fine. Is there a reason for this?

  Even if it works, this process is medium long and it's a waste of time because the DFD screws are already being implemented, so we need a quick fix for this, any suggestions.

  When you use the DLL that uses the DFD screws, it always seems to be a failure when loading the DLL file specific screws, anyone know why? Screw looking for Labview is in a way that looks at "DllFileLocation.dll------Labview 2009------vi.lib------...» "

  Thank you

  Walid Farid

  
  

• Integration of LabVIEW with SALT 421 specifically with regard to the measures of Phasor

  I want to get a relay SEL421 PMU data in labview system using ethernet. I am a beginner and do not have much experience with blocks of communication in labview. Can you please help me understand the concept and point me in the right direction.

  Hello

  -You must configure your device as a new resource VISA. Please click the link below:

  - New VISA resources TCP/IP

  -Once this is configured correctly, you must test your device by using the VISA test panels, once that part works, you can move to LabVIEW.

  Concerning