LV-functions modeling restrictions?

Hello

I use LabVIEW 2011 to create a model (.lvmodel) for Veristand 2011.

It works if I import a VI with only simple digital functions.

When I try to import a complex more a compilation process is abandoned.

Can what LV-functions I use in a model?

I am trying currently to use (with shift registers) while loops, queues, events, cases-structures, sequences, - number of cycles, numeric, Boolean and comparison of functions.

There are some variable clusters, DBL, I64 and U8.

I will study the possibility of using the Control Design and Simulation Module for a new design, but it would be very useful to know what went wrong.

Greetings

Frank

Thanks for the clarification. I think I see what's happening.

Models should be designed to run and end immediately. It should not be a loop in the VI which is repeated over time. VeriStand itself is responsibel for the planning of the model by which invokes several times every moment of the control loop (or some decimation of it). The general idea is that models will be simply a calculation based on the inputs and parameters and then publish the output data.

So, it seems that your model would simply be code background loop that does the calculations, but without the loop itself, since VeriStand serves as a loop. You can still have a loop in your model to take advantage of shift uninitialized registers to save state data between runs, but the loop must always have a real connected to a Terminal to stop.

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