Problem of transmission of the data of the object of the table via an IF statement

I have problems with a data member of an object passing a table via an IF statement.  In my function, if I just display the type of an object selected in the list, it will return trip or Fill-Up on the screen, which is correct.

If I use an IF statement to check the type first to see if it matches a string, it always by default the first game.  Suite of the code below, "it is a journey" always gets selected, even if the type matches "fill."

What I am doing wrong?

public void showEntry(e:ListEvent):void {}

clearWindow();

drawManageWindow();

If (e.data.type = "Trip")

{

clearWindow();

drawManageWindow();

var showtype:Label = newLabel();

ShowType.Text =

"Show trip."

ShowType.x = 500;

ShowType.y = 40;

ShowType.Height = 30;

ShowType.Width = 485;

addChild (showtype);

}

else if (e.data.type = "gas Fill-Up")

{

clearWindow();

drawManageWindow();

var showtype:Label = newLabel();

ShowType.Text =

"Show the Fill-Up."

ShowType.x = 500;

ShowType.y = 40;

ShowType.Height = 30;

ShowType.Width = 485;

addChild (showtype);

}

}

I'm surprised that the compiler is run, did disable strict mode?

For compare equality using ==

Tags: BlackBerry Developers

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    The problem I face is that I want to send three different tables, two of the same size and the third with different size, and I need one more small to be sent first to the FPGA. I tried to use encode dish with two executives in the FPGA VI. In the first image, I read and write the first table in a while loop which is finite (that is, a finite number of iterations). The second frame contains the process of reading and writing the second two tables (of the same size) in a while loop that can be finite or infinite (depending on a control). The problem is that it does not work. 2 arrays are displayed on the front panel of the RT VI host and works well, however, the table that should have been read in the first sequence does not appear on the front panel of the RT VI host. It is not sensible because if it is not passed from the host to the fpga and vice versa then the second image should not have been executed. Note that I'm wiring (-1) for the time-out period to block the while loop iterations until the passage of each item is completed. So the first while loop has only 3 iterations. Could someone help me undersdtand why this happens and how to fix this?

    I enclose a picture of the host and the fpga vi.

    Thank you.

    If you vote for my idea here and it is implemented, you can even omit the loop FOR fully.

    (I also propose the RE / IM divided inside the loop FOR and perform operations on complex table before the loop the transpose and reshape .) In this way, you only need one instance of these operations. You might even save some unnecessary allocations table in this way)

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