Validation for EPMA deployment error
Trying to to redeploy application EPMA after making a few changes to metadata we started getting the following warning messages in the journal of validation:
Caution details
===============
WARNING: The "Custom1" dimension has an invalid value of '0' for 'Custom size'. It must be a whole and not used by any other generic dimension.
WARNING: The "Custom2" dimension has an invalid value of '0' for 'Custom size'. It must be a whole and not used by any other generic dimension.
ATTENTION: The dimension 'Custom3' has an invalid value of '0' for 'Custom size'. It must be a whole and not used by any other generic dimension.
ATTENTION: The dimension 'Custom4' has an invalid value of '0' for 'Custom size'. It must be a whole and not used by any other generic dimension.
No idea why he started to occur and how to fix it?
Thank you, Igor
Hi Igor,.
There is a new property of Consolidation of EPMA with dimensions customized in 11.1.2.3 PSU 700 and 11.1.2.4. Sounds like you applied PSU 700 11.1.2.3 or transformed the classic or imported artifacts of 11.1.2.4 earlier. In any case, to resolve the problem, highlight each of the custom in the library of Dimension dimensions and view the properties of Consolidation. Set the field size in the order you want as shown below. Note: the "From" currency dimension must have the value 1 and the size of currency 'To' must have a value of 2. The others can be in any order.
Redeployment and you should be all set.
Thank you
Erich
Tags: Business Intelligence
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http://support.Microsoft.com/kb/938450
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http://support.Microsoft.com/kb/950756
Also see the following link for more information about reduced functionality mode:
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http://support.Microsoft.com/kb/925616/
Hope this information is useful.
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Microsoft Answers Support Engineer
Visit our Microsoft answers feedback Forum and let us know what you think.If this post can help solve your problem, please click the 'Mark as answer' or 'Useful' at the top of this message. Marking a post as answer, or relatively useful, you help others find the answer more quickly.
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Analysis of the dependence running...
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>
< 15 April 2009 13:47:33 IS > < WARNING > < hats > < BEA-149004 > < failures have been detected all introducing deploy application task "Evrak" >.
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>
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Libraries check on your project, jdev sometimes adds the projects of runtime libraries of Trinidad (or other libraries in the view layer) and creates a public_html folder in your project.
So, check the library and delete the public_html, if it is created.Pedja
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Deployment nirio_DMAReconfigureDriver.vi (16.63 K)
Deployment _nirio_device_writeBlock32.vi (9.36 K)
Deployment nirio_Read8.vi (13.04 K)
Deployment nirio_DMAStopAll.vi (11,39 K)
Deployment _nirio_device_attrGetString.vi (13.06 K)
NirviReportUnexpectedCaseInternalError (String) (5.58 K) .vi deployment
Deployment of .vi nirviReportUnexpectedCaseInternalError (U32) (4.72 (K)
Deployment _nirio_device_readBlock32.vi (14.41 K)
Deployment _nirio_device_attrGet32.vi (13.85 K)
Deployment nirio_IsItOKToDownload.vi (7.07 K)
Deployment nirio_MiteNTDeviceFamily.vi (5.30 K)
Deployment of Format Message String.vi (7.35 K)
Deployment CORE.vi General Error Handler (51,02 K)
General Error Handler.vi (13.19 K) deployment
Simple deployment Error Handler.vi (10.01 K)
Deployment nirio_CheckDriverVersion.vi (10,58 K)
Deployment _nirio_device_attrSet32.vi (13,62 K)
Deployment nirio_Download.vi (29,31 K)
Deployment nirio_ConfigureRegisterAddresses.vi (7.11 K)
Deployment nirio_CleanUpAfterDownload.vi (6.22 K)
Deployment nirio_PrepareForDownload.vi (6.44 K)
Deployment nirio_EnableInterrupts.vi (13.76 K)
Deployment nirviRIOSetUpMiniMite.vi (31.23 K)
Deployment nirio_Open.vi (14.93 K)
Deployment nirio_Close.vi (10.95 K)
Deployment nirio_DisableInterrupts.vi (11,10 K)
Deployment of nirviIntfOpen_cRIO - 9102.vi (85,54 K)
Deployment of nirviIntfClose_cRIO - 9102.vi (12.24 K)
Deployment of scale freq and duty.vi (4.46 K)
Deployment XDNodeRunTimeDep.lvlib
Deployment XDNodeRunTimeDep.lvlib:loadlvalarms.vi (5.47 K)
Math.vi sensor deployment
Could not download the math.vi sensor
LabVIEW: Resource not found.
LabVIEW: Resource not found.
LabVIEW: Resource not found.
LabVIEW: Resource not found.Download completed with errors.
This error message is not particularly useful, someone knows what could be my problem? Or how I can fix it yet? Is there a detailed journal where I can look for more information about the error?
Thanks in advance for any help!
Hi David,
You may be walking on ground dangerous with your fpga code, old and new. You use the modules in what is known as 'calibrated' calibration mode that is of fixed point math. Your generation of square wave fpga using whole math, which is normally used when the modules operate in mode calibration "gross". To change the calibration mode, you will need to right click on the module, then select it desired mode to use. I'm not saying that you do.
What you need TO do to ensure the proper functioning of your fpga VI is to make sure that you use U32 son of math required and then convert the U32 an FXP using the correct encoding (if it is signed, word length and integer). In your case the 9263 requires signed word in length, 20-bit, 5-bit all over. Insert an FXP conversion between the generation of square wave and either create a constant FXP of the appropriate type (or use a control correctly put in place of one of the other 9263 channels [AO0 AO1]) and connect to the node of type of fixed point on the conversion OR define the conversion of fixed point with a right click on the exit node and the appropriate settings in the popup box.
As for your new code fpga, I don't know why you used a sequence structure that your reading of 18 channels on the 9205 will have 144 microseconds, and each write two channels on the 9263 will take 5 microseconds. I've not worked on how long will take the square wave generation.
I do not understand your last question.
> "I've attached a screenshot of my pwm_out.vi if I remove control of read/write of background, or if I don't use of all none of the analog inputs, it works fine.
> But as soon as I add the analog inputs it fails... ».
Did you create a new stream of your fpga_new.vi and referenced in your pwm_out_new.vi on the RT?
It is difficult to guess what you are showing in the screenshots. If the project is not too big then maybe you could post here.
As mentioned above, by JMoto, software versions help. Check in MAX you have on your PC and also on the cRIO 9002 to make sure that there is no incompatibility.
See you soon
Stephen
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