Similar Questions

• On a Linux operating system, what tools need to developed a real-time application that communicates with FPGA?

  On a Linux operating system, what tools need to developed a real-time application communicating with FPGA?

  It is not unclear to me by reading the documentation on the website OR tools or drivers should I install on a Linux operating system in order to develop a C++ real-time application (that interact with FPGA) which will take place on a sbRIO-9651.

  Is this possible at all?

  Thank you

  Michel

  Everything works very well with an FPGA VI, compiled with LabVIEW FPGA 2015.

  1. I have installed Eclipse on CentOS 7 with cross-compiler found at this link:

  Compilers C & C++ GNU for Linux ARMv7 (Linux host) 2014

  2. I also install a debugger crossed to debug application c / c++ remotly. Once on the page go in the section "Linaro Toolchain for Cortex-A" and download the second link linux "linaro-toolchain-binary (big-endian).  The binary gdb is in there, so you must point towards him in the Eclipse debug configuration:

  Linaro Toolchain for Cortex-A

  3. I installed the linux drivers from NOR-RIO 15:

  Driver OR RIO 15.0 for Linux

  4. I was able to program an application to c / c++ opening and running a LabVIEW FPGA Bitstream in a few steps:

  Example of API Interface FPGA C OR real time Linux and Eclipse

  Michel

• Release NiFPGA 7842 DMA FIFO after reading memory

  Hello

  I use the card RIO de Ni7842. I've implemented a block for the acquisition of data on my FPGA (target device) and filling a FIFO to transfer the data from the target to the host machine. I've implemented the FIFO to a size of 10 k. The number of samples that I'm gaining is 16 K on three channels simultaneously.

  I read the data from the FIFO DMA implemented on a host machine with the support of the C API for the Council. I have setup the FIFO for read in three steps by launching calls to methods:

  -ConfigureFIFO - configure FIFO depth

  -FIFO reading - read items in a host DMA - it runs in a loop playback of 1 k datapoints at each iteration (the data type I16's not 2kb which is playing)

  -Stop the FIFO

  What is the memory allocated on the host DMA by calling method configureFIFO need to be released explicitly by calling ReleaseFIFO? Note that AcquireFIFO is not called here.

  Please advice.

  Thank you!

  In my view, all memory is allocated out during the call to NiFpga_Finalize, but I was not able to find a specific documentation to confirm that.

  There is a specific example of FIFO included with the C API of FPGA that my be of interest to you if you have already looked at him.

• Error-63101 when executing the FPGA Interface C API Generator in LabVIEW 2012

  I'm using LabWindows CVI 2012 and 2012 LabVIEW FPGA module.  I try to use the FPGA Interface C API generator and I get the following error from a freshly generated .lvbitx bitfile.  I use the local server compiles on my PC.

  Error-63101

  NOR-RIO: A valid .lvbitx bitfile is required. If you are using a valid .lvbitx bitfile, the bitfile maybe isn't compatible with the software you use. Determine which version of LabVIEW was used to make the bitfile, upgrade your software to this version or later, and then try again.

  The problem occurs when executing CVI or LabVIEW.  I was able to do this earlier when I was compiling the FPGA in LabVIEW with the API generator 2011 downloaded from the Web site.

  A bit of weirdness in my setup, it's that I charged it off downloads from the website (latest files after 2012 NIWeek) rather than the normal distribution DVD.  I installed LabVIEW, so NI RIO, then the Xilinx tools compatible with 2012.  It works very well when you talk to the FPGA to a LabVIEW vi running on my Windows PC to the host.

  Any suggestions?

  Problem solved.  I had to download FPGA Interface C API generator 12.0.  It works now.

  I would have thought that if a product was called on the menu in LabVIEW 2012, it would be prompted to upgrade to a compatible version, when I installed LabVIEW.  The old version is not compatible with version 3.0 bitfiles, as identified on the following lines at the top of the .lvbitx file:

  
  
   3.0

• FPGA Interface C API, error-63105, OR-RIO: C/C++ identifier is already in use and cannot be created.

  Hello

  Installation program:

  1 x the NI PCIe-7841R

  When I am trying to automatically generate a C++ API for my top FPGA VI using the FPGA Interface C API 12.0 I get the following error.

  Error-63105

  NOR-RIO:

  The "NiFpga_FPGATop_IndicatorBool_DMAFIFOtimeoutoccured" C/C++ identifier is already in use and cannot be created.

  Anyone know what this means? Is there some kind of limitation on the appellation of front interface controls?

  /Mola

  Problem solved.

  I had placed two flags with the same name on the front panel - by mistake. It builds the FPGA without errors, but the C API generator was not in favour of that.

  / Mola

• Safe multithreading NI FPGA Interface C API?

  Hello

  I use the FPGA C API interface to communicate with the software labview on my FPGA OR. Some calls take a while to run, for example, reading on a FIFO so long timeout. So far, I assumed that the interface was not safe multithreading. It has now become annoying given the timeout problem described above. Try simply was not good, it can take a long time to create a "collison.

  Is the FPGA interface safe multithreading C API? Or, more specifically, the functions of FIFO reading can be called in parallel with read/write variables on the FPGA?

  Thank you.

  Hello MKAP,.

  It has been a while since I used the NI FPGA Interface C API, but it is what I remember and seem to be able to remember (and also found in the documentation):

  Functions related to the unloading and loading of the library are not thread-safe:

  http://zone.NI.com/reference/en-XX/help/372928D-01/CAPI/functions_required/

  On itself, this should be a problem:

  Your application should require that the NiFpga_Initialize is called before any other function associated with function calls NIFpga.

  In a similar way that unloading (NiFpga_Initialize) lof NiFpga brary should occur only when you are finished using it.

  With regard to multithreading, you must also keep in mind its mono-thread interrupts IRQ (if you plan to use them):

  http://zone.NI.com/reference/en-XX/help/372928D-01/CAPI/functions_interrupt/

• General questions about FPGA Interface C API 2.0

  I developed an application in LabVIEW FPGA 2011 on a Board of the R-Series PXI and a host application LabVIEW 2011 Windows XP to communicate with him via DMA FIFO.  I'm trying to adapt the interface to CVI 8.1 (preferred) or CVI 2009 using the Interface of FPGA C API 2.0.  The example of FIFO that it stores in the directory C:\Documents and Settings\All Users\Documents\National Instruments\FPGA Interface C API\Examples\ gave me a few questions:

  1. The functions NiFpga_WriteFifoI16 and NiFpga_AcquireFifoWriteElementsI16 are two different ways to do the same thing? I wasn't clear where I do the extra copy if you use NiFpga_WriteFifoI16. I guess the combination of NiFpga_AcquireFifoWriteElementsI16 with NiFpga_ReleaseFifoElements is the way to go if I want to stay out of trouble.
  2. I intend to call NiFpga_Initialize and NiFpga_Open in an initialization function that gives the word initially, then keep the session handle in calls to other functions.  The session handle is always not null when it opens successfully?  Could I use it as a test to make sure that I have a session valid before calling any other functions-example:
     If (session) {NiFpga_WriteFifoI16 (...)}
  3. Interface of FPGA C API 2.0 is only announced work in CVI 2009 up on.  If I include NiFpga.c and .h in my project CVI 8.1, it seems to compile fine, but I did have the chance to integrate yet.  Is there something specific that would make CVI 8.1 not work?  Our deployment environment of difficult application CVI upgrades

  -Jim

  Jim,

  With regard to your questions:

  1. Yes, these two functions are the same, however there is a big difference between the two. NiFpga_AcquireFifoWriteElementsI16 acquires, prepares and publishes FIFO elements to avoid the need to write the first in a buffer allocated by the separate user, then copy the contents of the elements in the memeory host buffer. Considering that, in the NiFpga_WriteFifoI16 does not work. So the NiFpga_ReleaseFifoElements should always be used with the NiFpga_WriteFifoI16. The example is just showing how the code should be used, but is not necessarily displayed works should be used together. I understand perfectly why he was confusing.

  2. the best way to ensure you have a valid session is by using the NiFpga_IsNotError() function. I've attached a screenshot of the example code that illustrates how best to achieve this and inserted the image below.

  

  3 regarding using CVI 8.1, there is nothing in particular, which would make your code does not work in point 8.1, but we can guarantee that C API 2.0 will work correctly with 9.0.

  Kind regards

  Larry H.

• Version of the C API for LabVIEW FPGA 2011

  What is the version of the C API that will work with LabVIEW FPGA 2011?

  I guess as this one: http://www.ni.com/download/fpga-interface-c-api-2.0/2616/en/

  Version numbers seem to start by 2012 years.  It's the latest version I could find before 2012 and he was released in August 2011.  This time coincides with the annual festivities of the NOR week where a large part of the software/hardware is released.  It's a small download, so it shouldn't be difficult to download it and try it.

  But, you'll still need LabVIEW FPGA development according to this white paper: http://www.ni.com/white-paper/9036/en/

• SMU 7857R FPGA and DAQ task

  I'm looking at the SMU 7857R.  I would use the 8 analog inputs and the FPGA to do some annalysisy and DIO based on the best data.  I was wondering if it is possible to also define a DAQ task so that all analog data will be made available to the host.  Using a data acquisition task would be easier for me to have to write code fpga for use a DMA fifo to send back data.

  Hi bcat!

  A data acquisition task is only for devices Data Acquisition product supported by driver DAQmx as X-, M-, S-, maps E-Series. The boards of the R series are only supported by the driver OR RIO.
  If you don't need pre-treatment on the FPGA so that you can distribute simple data through DMA on your host. If you are looking for an API for the comparable FPGA with the DAQmx API then please check the NI CompactRIO waveform reference library. You can also use the library for R Series boards.

• The create a System Image will save the FPGA code and the RT code?

  I have some cRIO systems which were broadcast in our manufacturing plant for some time. A slight problem has been discovered in the programming and created a workaround solution, but a fix should be implemented. Currently, I have no way to test my new code without loading on the cRIO and it works on the tool while the product is running. If there is a problem and I need to do some debugging, the tool cannot be down for an extended period. I would write a vi that will save an image of the cRIO so I can reload the software that is currently running and prevent a situation of prolonged downtime.

  My question is, when I did in the past with a product that has different tests, calibration and the final client software RT, it seems that the code FPGA not be saved (not a big deal at the time since the new FPGA code was compatible with different deployments RT). The new FPGA code won't be compatible with the old RT software, so now I'm worried. I would like to just check on it until I have all the boss breathing down my neck. If the service will not save the bitfile FPGA, is there anything else I can do for the tool to return to the previous running state while I solved problems that may exist with the new code review? The original code was lost by my predecessor. Otherwise, I would use just that.

  Hi Jeremy,.

  You are right, because the create a System Image does not record the bitfile with the image of the RT. Using the configuration system API, you will need to deploy the RT image and then the bitfile FPGA compiled later. To ensure that you can return to the previous version of the software running on your RIOs, you could simply save the current image and bitfile before deploying the new image and bitfile.

  However, the best way to proceed is to use replication Deployment Utility (RAD of OR). I have provided the link to the tutorial on the wheel, where you can download the utility. This exe will make images of the any of your RT targets and will also include the bitfiles with them. You can also deploy these images to several targets at once. In particular, you can read about the Bitfile (s) configure for FPGA Deployment Flash; the bitfile will be deployed at the start when stored in flash memory.

  Replication and deployment (RAD) utility-

  http://www.NI.com/example/30986/en/

• Issue of Python API and profile of Stimulus

  Hello

  I am using IronPython with Visual Studio 2010 to create automated tests of a PXI system I have. Most of my knowledge API (and Python) so far has been coming to this thread of Iron Python . Although very useful. I am not able to get the parts of profile of Stimulus work. I have command over the line, forcing the acquisition of basic data output voltage, but I was hoping that use the far more high-level control provide by VeriStand.

  My methodology so far has been 1) create a profile of Stimulus in the Editor (something simple like a shifted sine wave) 2) I do not specify a specific channel in the profile (because I want to use the same waveform on several channels, in order) 3) record 4) Point the Python script to the sinewave.nivstest of the file Run 5). Is there something wrong with this process?

  The problem is that 'running' is really doing nothing. I'll have to study this more within my reach, but the result is something (it begins almost at work!) but for something that should be hard about 20 seconds, it ends immediately after the first 'blip '.

  I use Iron Python 2.7, VS 2010 Shell. If it's important for some reason, I use a custom material OR and card FPGA DAQ. And I would say force SetChannelValue (X) works for all outputs.

  Thank you very much!

  It's probably because you're playing a stimulus that has no mapping. The same thing happens if you specify a mapping in the profile?

  Unfortunately, there is no API in NI VeriStand in 2010 to change the mapping. So that's all that you specify when you create with the GUI. However, the nivstest file is actually just XML so that you can use any XML parsing and API for editing to change the mapping. If you don't want to use an API for XML editing, you can try to use the technique in the VI posted on this thread to change the mapping.

• FPGA configure trigger

  Quick question: how to set up the trigger in the FPGA C API interface?

  More details:

  I'm looking to interface a NC (7965R) via the function Matlab MEX (C).  I programmed most of FPGA functions, including NiFpga_ReadXXXX functions, the functions of FIFO configuration, etc.   I call NiFpga_Initialize, NiFpga_Open, and they return status 0.   Functions return with a status of 0 NIFpga_ReadArray, but they don't return meaningful data (of zeros).

  However, there is a feature that appears in our Labview code that I can't seem to find an interface C equivalent to, and it is a function to set the trigger.  Small is important because our FPGA is triggered externally.   When I call the functions of ReadFIFO I get a timeout, no matter how long a timeout or how small of a buffer I give him.  In my opinion, because relaxation is misconfigured somehow.

  Update: OK, in relaxing configure VI, which they call a "read/write control" VI, I guess that means, it calls a function of NIFpga_WriteXXX?

  The conversion wizard wasn't able to convert the cluster because there is not an exact correlation in C.  The nearest representation would be a struct.  Change to a series of values is probably the best option unless your structural elements are of the same data type.

• Research of interface software for FlexRIOs using API c do I need LabVIEW once I use the C API generator?

  Current versions of software:

  LabVIEW 2014 SP1

  LabVIEW FPGA 2014

  Xilinx Vivado

  Hi all

  I plan to interface my FlexRIOs to the software programmed in C, then the C API FlexRIO is excellent.

  My question is more economy of memory sake.

  I have a PC with Visual Studio, I want to add the minimum amount of software development.

  If I have a station (a separate Visual Studio PC PC) FPGA development with all LabVIEW software necessary to take the step of the use of the generator of the C API to create the necessary files of C and H, should what software I on the development PC Visual Studio in interface with the files in the generated C API?

  If all goes well, it's just (from the help)

  What you need to get started

  • Drivers for devices OR RIO August 2013 or later

  However... The help of the C API, it gives me the full list of the software including LabVIEW and LabVIEW FPGA... (below)

  What you need to get started

  In addition to a RIO device like a CompactRIO reconfigurable chassis, a Single-Board RIO device or RIO PCI or PXI hardware, you need the following software to use FPGA Interface C API.

  • LabVIEW 2009 SP1 or later (32-bit only)
  • LabVIEW FPGA Module 2009 SP1 or later (32-bit only)
  • Drivers for devices OR RIO August 2013 or later
  • Operating system supported development
    • Windows 8 or 8.1 (32-bit or 64-bit)
    • Windows 7 Professional (32-bit or 64-bit)
    • Windows Vista Business (32-bit or 64-bit version)
    • Windows XP Professional SP2
    • Windows Server 2008 R2 (64-bit version)
    • Windows Server 2003 (64-bit version)
  • Target supported OS
  • Supported C/C++ compiler

  So I have LabVIEW and LabVIEW FPGA on the development PC?

  (If all goes well no....)

  Thank you

  Hey Colonel1013,

  With the C API, you only need LabVIEW to build a bitfile and run the generator of C API tool, but LabVIEW is not required to run. That is, you need all the software listed, but it must not all be on the same machine. You can transfer the file lvbitx and the .c and .h files generated on another machine where you need only NOR-RIO and Visual Studio installed.

  Sebastian

• SoftMotion and FPGA OR 9514

  Hey Gang,

  I spent the day to set up a new system of cRIO and a new installation of LV2012 RT and FPGA Softmotion.

  Our system uses a CAN interface, which, we learn, requires the use of FPGA mode.  Maybe this isn't a bad thing, because we are concerned about the speed of the scan mode.  I developed an FPGA application before.

  My main concern is right now, to get the job of control of movement stuff.  Our movement is a NI - 9514.  I hope there is a way to use the SoftMotion modules with the FPGA interface. Otherwise, the movement FPGA examples look REALLY discouraging!

  All I do is homing and simple relative motions.  I enjoy all help/advice on the simple/fast way to get there.

  Thank you!

  Roger

  Hi Roger,

  You can use the 9514 without using the "formidable" examples using the cRIO in hybrid mode. There are good instructions on how to do it here. A quick summary, is to put the modules you want to use in scan mode under the chassis and modules you want to use FPGAS in the FPGA. When you compile the FPGA bitfile, RIO scan interface is compiled for modules that are under the chassis so that you can use in scan mode. A few warnings:

  • The FPGA VI must be running to use the 9514. When you are in scan mode, the FPGA runs automatically without requiring you to do so. However, in hybrid mode, the FPGA does when you run it explicitly.
  • The FPGA VI should work for deploy you the settings of the axis of the target. This can be a bit awkward during development when you make changes to the configuration of the axis. Usually, you run the FPGA VI using the open FPGA VI reference in a RT VI. However, when you run a RT VI, it checks to see if the deployed data are compatible with the project data and if not, invite you to deploy. Don't forget, however, that you cannot deploy your FPGA VI because is not yet running (since it won't work until the open FPGA VI reference runs). When you try to deploy, you will get an error (I think it's something like "E/s Module not found"). What I do usually is during development, run the FPGA VI manually (by pressing the run button). You can then run your VI RT which uses the FPGA VI reference and everything will work. You will encounter this problem only if you change the configuration of the axis of the project (and so won't be a problem for your final application when changing your aern can't axis settings). If you change the configuration of the axis programmatically, you do not experience this problem.

  As a note side for those who use the 951 x modules of movement, unless you really need to do something custom, you must use the modules of 951 x in scan mode. The performance is better in scan mode it is using FPGA (assuming you want to use the API SoftMotion high level (EXVIs, blocks of functions or properties/methods)). When you use FPGA mode, there is further delay to obtain the data of the FPGA in the SoftMotion engine. In addition, you are always coupled to the scan engine! If you get the worst performance, a more difficult experience, and you don't even remove the need for the analytical engine. There are valid reasons to use the modules of 951 x on the FPGA (for example custom control loops), but most applications I've seen use FPGA would be better served by using the module in scan mode.

  Thank you

• FPGA read/write eeprom I2C

  Someone at - it an example of LabVIEW for I2C communication to read/write an eeprom?

  I use sbRIO-9636 with FPGA.

  I already tried with the "Advanced I2C" example, but it works...

  Can someone help me?

  Another suggestion:

  You know about the VI package manager? There, you can install an application open source I2C & SPI API (worms. 3.0.0.22). It is an easy way to implement a system of Bus I2C on an FPGA target.

  In this way is a little bit smarter.

  Maybe you like it.