Safe multithreading NI FPGA Interface C API?

Similar Questions

• Error-63101 when executing the FPGA Interface C API Generator in LabVIEW 2012

  I'm using LabWindows CVI 2012 and 2012 LabVIEW FPGA module.  I try to use the FPGA Interface C API generator and I get the following error from a freshly generated .lvbitx bitfile.  I use the local server compiles on my PC.

  Error-63101

  NOR-RIO: A valid .lvbitx bitfile is required. If you are using a valid .lvbitx bitfile, the bitfile maybe isn't compatible with the software you use. Determine which version of LabVIEW was used to make the bitfile, upgrade your software to this version or later, and then try again.

  The problem occurs when executing CVI or LabVIEW.  I was able to do this earlier when I was compiling the FPGA in LabVIEW with the API generator 2011 downloaded from the Web site.

  A bit of weirdness in my setup, it's that I charged it off downloads from the website (latest files after 2012 NIWeek) rather than the normal distribution DVD.  I installed LabVIEW, so NI RIO, then the Xilinx tools compatible with 2012.  It works very well when you talk to the FPGA to a LabVIEW vi running on my Windows PC to the host.

  Any suggestions?

  Problem solved.  I had to download FPGA Interface C API generator 12.0.  It works now.

  I would have thought that if a product was called on the menu in LabVIEW 2012, it would be prompted to upgrade to a compatible version, when I installed LabVIEW.  The old version is not compatible with version 3.0 bitfiles, as identified on the following lines at the top of the .lvbitx file:

  
  
   3.0

• FPGA Interface C API, error-63105, OR-RIO: C/C++ identifier is already in use and cannot be created.

  Hello

  Installation program:

  1 x the NI PCIe-7841R

  When I am trying to automatically generate a C++ API for my top FPGA VI using the FPGA Interface C API 12.0 I get the following error.

  Error-63105

  NOR-RIO:

  The "NiFpga_FPGATop_IndicatorBool_DMAFIFOtimeoutoccured" C/C++ identifier is already in use and cannot be created.

  Anyone know what this means? Is there some kind of limitation on the appellation of front interface controls?

  /Mola

  Problem solved.

  I had placed two flags with the same name on the front panel - by mistake. It builds the FPGA without errors, but the C API generator was not in favour of that.

  / Mola

• General questions about FPGA Interface C API 2.0

  I developed an application in LabVIEW FPGA 2011 on a Board of the R-Series PXI and a host application LabVIEW 2011 Windows XP to communicate with him via DMA FIFO.  I'm trying to adapt the interface to CVI 8.1 (preferred) or CVI 2009 using the Interface of FPGA C API 2.0.  The example of FIFO that it stores in the directory C:\Documents and Settings\All Users\Documents\National Instruments\FPGA Interface C API\Examples\ gave me a few questions:

  1. The functions NiFpga_WriteFifoI16 and NiFpga_AcquireFifoWriteElementsI16 are two different ways to do the same thing? I wasn't clear where I do the extra copy if you use NiFpga_WriteFifoI16. I guess the combination of NiFpga_AcquireFifoWriteElementsI16 with NiFpga_ReleaseFifoElements is the way to go if I want to stay out of trouble.
  2. I intend to call NiFpga_Initialize and NiFpga_Open in an initialization function that gives the word initially, then keep the session handle in calls to other functions.  The session handle is always not null when it opens successfully?  Could I use it as a test to make sure that I have a session valid before calling any other functions-example:
     If (session) {NiFpga_WriteFifoI16 (...)}
  3. Interface of FPGA C API 2.0 is only announced work in CVI 2009 up on.  If I include NiFpga.c and .h in my project CVI 8.1, it seems to compile fine, but I did have the chance to integrate yet.  Is there something specific that would make CVI 8.1 not work?  Our deployment environment of difficult application CVI upgrades

  -Jim

  Jim,

  With regard to your questions:

  1. Yes, these two functions are the same, however there is a big difference between the two. NiFpga_AcquireFifoWriteElementsI16 acquires, prepares and publishes FIFO elements to avoid the need to write the first in a buffer allocated by the separate user, then copy the contents of the elements in the memeory host buffer. Considering that, in the NiFpga_WriteFifoI16 does not work. So the NiFpga_ReleaseFifoElements should always be used with the NiFpga_WriteFifoI16. The example is just showing how the code should be used, but is not necessarily displayed works should be used together. I understand perfectly why he was confusing.

  2. the best way to ensure you have a valid session is by using the NiFpga_IsNotError() function. I've attached a screenshot of the example code that illustrates how best to achieve this and inserted the image below.

  

  3 regarding using CVI 8.1, there is nothing in particular, which would make your code does not work in point 8.1, but we can guarantee that C API 2.0 will work correctly with 9.0.

  Kind regards

  Larry H.

• NEITHER 9512 with Labview FPGA Interface

  Is it possible to use the NI 9512 stepper with Labview FPGA interface drive unit or is it only possible to use it with the interface of scanning? When I try to add the module to a FPGA target, I get an error telling me that Labview FPGA does not support this module with the latest version of NOR-RIO, but I have the latest version of OR-installed RIO.

  Hi Checkit,

  You're right - the 9512 cannot currently be used in FPGA. There is an error in the documentation. The 9514 and 9516 can, however.

• Sharing of Variables does not not under an FPGA interface?

  Hi all

  I have a controller 9074 cRIO 9074 chassis.

  I defined a number of variables shared under my RIO controller and writing a UI VI in my host PC, where I feed some variables of network shared in RIO and get another return to RIO on the front panel of my host. Naturally, the VI which deals with read/write variable network data to IO channels real is under my RIO controller.

  The problem is that, although everything seems to work fine when my RIO is set to the interface of the Scan Engine, the same screws give the following error message when I pass my RIO FPGA interface dependent.

  -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Possible reasons:

  CompactRIO: (Hex 0xFFFF0000) unable to communicate with the module. Re-insert the module and check the connections. If the chassis is in Interface FPGA programming mode, make sure that you have opened a FPGA reference bitfile or VI FPGA with the load of the Interface of scanning for the module you are trying to access using the scanning Interface.

  This error or warning occurred when writing the following shared Variable:
  \\AMR-cRIO9074\B1-DO\JCV1_C1_B1
  \\160.40.15.231\B1-DO\JCV1_C1_B1

  -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

  Note that I get this error message for each channel of e/s that I call my RIO. Also note that it is there still no reference FPGA currently in any of the screws... I want to solve the problem is because later, I'll have to add some FPGA in my code, so I can not just impersonating my RIO scan interface...

  Any help would be appreciated,

  Harry

  When you disable scanning on the cRIO platform engine, you must have some runing FPGA code.

  There is noway that knows your controller on any module, and he can't read anything from any module.

  If you do not have an FPGA vi, which sends the values of a port of the module on your controller, you need to do active Scan Engine.

  The error message clearly indicate that you must have an open reference FPGA vi or analytical engine to be able to read the values of and to a module.

  You are able to have custom analysis engine and a footstool of FPGA code at the same time on an FPGA.

  Is there a reason you do not run with the scanning engine?

• Control of read/write of FPGA Interface

  I need help on control of FPGA read/write Interface. I would like to connect data TCP Read (String) directly to VI FPGA Read, but the entrance is an FXP... How can I do this?

  Then change your FPGA control to be a byte (U8).  On the side of your host, use the array of strings of bytes, then Index Array to get the specific byte you want to write on the FPGA.

• FPGA Interface Cast question

  I play with a VST 5644 and model VST streaming.  On the FPGA VI, I added the code, then added an indicator of the face before of the FPGA VI and compiled.  Executes the FPGA VI in interactive execution mode, the indicator works well.  Side host, however, I can't access the new indicator with read/write control.

  Coming out of the open FPGA VI reference I can see the indicator on the wire, but in the Dynamic Cast of Interface FPGA function is have rooted out the refnum somehow.  If I connect to control read/write directly to the output of the function of open reference I can access the indicator very well.

  No idea what I am doing wrong?

  Thank you.

  You re-configured your FPGA VI reference with the new bitfile interface?  The cast of dynamic interface defines the lead as all methods and indicators according to the type of wire connected.  You can right click on the constant of type and select "Configure the FPGA VI... of reference".  In the pop up window that follows, select "import of bitfile...". "and select the new bitfile you've built.

  You must update the fpga reference type in the "Device Session.ctl" type def as well.  This is the type that you will be able to access throughout the project.

  

• Create Source for Interface - using API

  You will need to create source for newly created using API interface.
  
  Tried it with code, get below error below
  
  During the synchronization of a new object was found through a relationship that was not marked cascade PERSIST:
  
  Please help on this, thanks.
  
  Here is my code component,
  
  
  The list of ds < DataSet > = next_intr.getDataSets ();
  < DataSet > iterator itr = ds.iterator ();
  DataSet ds_nxt1 = itr.next ();
  String ds_name = ds_nxt1.getName ();
  If (ds_name.equalsIgnoreCase (ds_nxt. GetName()))
  {
  Collection < SourceDataStore > ds_sources = ds_nxt.getSourceDataStores ();
  ds_nxt1.addSourceDataStore (ds_sources. Iterator(). Next());
  }

  http://odiexperts.com/creating-permanent-interface-based-on-model-level-2/

  http://odiexperts.com/creating-interface-for-single-source-and-target/

• Broken thread - FPGA Interface Node error

  Hello

  I am programming my application of RT and I get this weird error:

  

  As you can see, I'm trying to set the value of a FPGA control (which is a typedef enum) and I get this strange cut wire

  for me, error.

  I was looking for a solution in the forums but I luckily able to get a... Could someone help me?

  Thank you!!

  PS: The error message was "the type of sink is zero" that is false, as already defined in the FPGA vi.

  Solved.

  To the right, it was like if I've changed some of typedefs and who did not have in mind. Recompiling solved the problem.

• FPGA interface of data acquisition

  I have a repetitive loop in a PXI-7813R producing reasons. The output of the PXI-7813R is TTL, but I need 0-15V levels. In the same PXI chassis, I have a DAQ (PXI-6528) hardware that can handle the voltage levels. The question is, can I somehow link the the 6528 7813R patterns using PXI backplane and leave this market while I wear the use of PXI rack for other functions?

  Thank you

  Andy Quick

  The problem with the PXI-6528, is that it is software programmed.  Which means trigger won't help you here.

  What you need to do is to do some work of material.  You can have the PXI-7813R output profiles and drive an opto-coupler or FET circuit to change the level of voltage of 15V.  Or maybe there is there a digital stamp which can output 15V for you.

• API C FPGA

  Hello

  I can generate a C API interface for FPGA design in Labview Communications.

  And how does it work?

  Thank you

  Sebastian

  Hi Sebastian,.

  If it is anywhere in the LabVIEW Communications, he'll be in tools Launcher. If it is not there then you can still generate a C API for your FPGA using the FPGA Interface C API generator. I received this the generating a C API for a help Application LabVIEW FPGA Document.

  Generating a C API in the Windows Start Menu

  
  

  Follow these steps to generate a C API for a bitfile compiled in the Windows Start menu.

  1. "" "" Select Start "all programs" National Instruments "FPGA Interface C API" FPGA Interface C API generator.
  
  
  2. On the Generator of API C FPGA Interface dialog box that appears, navigate to the compiled FPGA bitfile or type an absolute path for her.
  
  
  3. Select a directory for output to the C API. If you do not select an output directory, the files in the C API will be created in the directory that contains the bitfile. You can navigate to a directory or type an absolute path for her.
  
  
  4. Optionally, you can change the prefix for the generated files and constants in the generated .h file.
  
  
  5. If you are using LabWindows/CVI to develop your C application, check next to exclude NiFpga.h/NiFpga.cas FPGA Interface C API installs the header and library files with the support of LabWindows/CVI.

  Make sure you have installed FPGA C Interface API .

  Introduction to the API of C Interface of FPGA

  See you soon

• Research of interface software for FlexRIOs using API c do I need LabVIEW once I use the C API generator?

  Current versions of software:

  LabVIEW 2014 SP1

  LabVIEW FPGA 2014

  Xilinx Vivado

  Hi all

  I plan to interface my FlexRIOs to the software programmed in C, then the C API FlexRIO is excellent.

  My question is more economy of memory sake.

  I have a PC with Visual Studio, I want to add the minimum amount of software development.

  If I have a station (a separate Visual Studio PC PC) FPGA development with all LabVIEW software necessary to take the step of the use of the generator of the C API to create the necessary files of C and H, should what software I on the development PC Visual Studio in interface with the files in the generated C API?

  If all goes well, it's just (from the help)

  What you need to get started

  • Drivers for devices OR RIO August 2013 or later

  However... The help of the C API, it gives me the full list of the software including LabVIEW and LabVIEW FPGA... (below)

  What you need to get started

  In addition to a RIO device like a CompactRIO reconfigurable chassis, a Single-Board RIO device or RIO PCI or PXI hardware, you need the following software to use FPGA Interface C API.

  • LabVIEW 2009 SP1 or later (32-bit only)
  • LabVIEW FPGA Module 2009 SP1 or later (32-bit only)
  • Drivers for devices OR RIO August 2013 or later
  • Operating system supported development
    • Windows 8 or 8.1 (32-bit or 64-bit)
    • Windows 7 Professional (32-bit or 64-bit)
    • Windows Vista Business (32-bit or 64-bit version)
    • Windows XP Professional SP2
    • Windows Server 2008 R2 (64-bit version)
    • Windows Server 2003 (64-bit version)
  • Target supported OS
  • Supported C/C++ compiler

  So I have LabVIEW and LabVIEW FPGA on the development PC?

  (If all goes well no....)

  Thank you

  Hey Colonel1013,

  With the C API, you only need LabVIEW to build a bitfile and run the generator of C API tool, but LabVIEW is not required to run. That is, you need all the software listed, but it must not all be on the same machine. You can transfer the file lvbitx and the .c and .h files generated on another machine where you need only NOR-RIO and Visual Studio installed.

  Sebastian

• Version of the C API for LabVIEW FPGA 2011

  What is the version of the C API that will work with LabVIEW FPGA 2011?

  I guess as this one: http://www.ni.com/download/fpga-interface-c-api-2.0/2616/en/

  Version numbers seem to start by 2012 years.  It's the latest version I could find before 2012 and he was released in August 2011.  This time coincides with the annual festivities of the NOR week where a large part of the software/hardware is released.  It's a small download, so it shouldn't be difficult to download it and try it.

  But, you'll still need LabVIEW FPGA development according to this white paper: http://www.ni.com/white-paper/9036/en/

• To refer to a table control FPGA

  I develop a cRIO application that includes a table of 23 controls in the FPGA.  The generator of FPGA Interface C API them defined as a name and size.

  typedef enum
  {
  NiFpga_ControlArrayU32_Setpoints = 0 x 8118,
  } NiFpga_ControlArrayU32;

  typedef enum
  {
  NiFpga_ControlArrayU32Size_Setpoints = 24,
  } NiFpga_ControlArrayU32Size;

  How do I référenceriez the 15th point, as NiFpga_ControlArrayU32 [15] or as an offset to 0 x 8118?

  Hi Paul_Knight,

  When the C headers are generated, there should be one called NiFPGA.h.

  There is a function within this header to read a U32 matrix. The function is called NiFpga_ReadArrayU32. This is a documentation on the different functions of reading table.

  http://zone.NI.com/reference/en-XX/help/372928G-01/CAPI/functions_readarray/

  You should be able to read the values in the table and store them in an array in C. You can then access them as you would normally in your program C. I hope this helps!