DIO using loop to generate TTL

Hello

I have a sbRio and on the FPGA, I have a loop that runs every 5 US. The loop has a counter that increments with each iteration, and I acquire analog data each cycle (effectively setting the rate to 200kS/s). The counter is used to generate a Boolean value True or False. Thus, for example, if the count is less than 200 (for example) the value is False, but greater than 200, it's true. The counter then resets back to zero in, say, 400. This counter is used for two purposes - the resulting value of T/F is sent to a DIO port then it becomes, in effect, a TTL output, and because I store the meter with the analog data, it acts as a reference for where the data were sampled in the cycle TTL.

My problem is that when I look at the output "TTL" on an oscilloscope everything seems pretty OK... except that now and then I get a glitch where it suddenly either falls to zero or "stutters".

The question I have is this - if I write a True value for a port DIO in a timed, loop makes this "lock" of value until it is changed or does literally flick on then turned off during a period of time (the implication being that it is actually not a true continuous, but a series of true/false steps which occur on a timescale much shorter than my loop time)? If so, is there a way to make sure the value remains constant until the next iteration of the loop? If this isn't the case, then should I move using ticks rather than at the loop timer?

Thanks (and sorry for the length).

I think the question is read the values half/full cycle. If I replace those with constants, the problem seems to disappear. I moved the reading of those outside the main loop, and that seems to have worked.

Thanks for your help! The loop of the case has been deleted since, as you pointed out, it was not necessary. Oh and sorry for the twisted...

Tags: NI Software

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redo size                                                              3132

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