FPGA IP core with verilog

Similar Questions

• MicroBlaze soft core with Spartan-3F kit

  Hello guys,.

  Is it possible to implement a Microblaze soft core with kit-LABVIEW FPGA and Spartan-3E? Examples?

  In addition, examples of executing a Picoblaze soft-core on Spartan-3E and using LabVIEW FPGA CLIP node kit? Thanks in advance!

  This link points to a generation on the Virtex 5 FPGA platform.  In principle, the process is the same for Spartan...

  http://decibel.NI.com/content/docs/doc-8753

• Can I upgrade my laptop cq56 Pisario Compact a 2.6 Ghz quad core with 4 GB of ram

  Hi Hp community.

  I am tring to get a new model on my computer called nolimits coaster 2 software. I had the demo and it runs pretty slow. I don't know if it's a memory or a CPU thing but I would love to get this without having to buy a computer brand new if possible. Here are their requirements: Windows 7 or newer, 2.6 GHz Quad Core with 4 GB of RAM, compatible Direct x 9.0 c (Shader Model 3) with 1 GB of video RAM

  Thank you, Michael

  Hello

  The following link shows the specifications of your computer:

  http://support.HP.com/us-en/document/c02636087

  As you can see, no way you can upgrade your machine for video 1 GB of RAM you given cannot go to 2.6 GHz CPU (maybe not image) and 4 GB of RAM. You buy the new machine to meet the requirements.

  Kind regards.

• CORS with ADF

  Hello

  JDEV version 11.1.1.7.0

  We strive to implement the CORS with domain CDN to be kept in the static content web server.

  We have added the Access-Control-Allow-Origin * in the file httpd.conf of OHS (11.1.1.7.0)

  The header seems to work very well with the CSS files and the police. But it fails for AJAX to JS calls.

  Does anyone have an idea what can be done?

  Here's the header added to the httpd.conf file

  < FilesMatch ".» (eot | ttf |) OTF | woff | JS | CSS) ">"
  Header value Access-Control-Allow-Origin "*".

  Header set Access-Control-allow-Headers:original Message, X-requested-with, Content-Type, Accept, Adf Rich
  < / FilesMatch >

  Thanks draio.

  This link helped.

  but my problem was the lack of "-" in the Message of Rich Adf.

• LabVIEW RT/FPGA Compling error with NI_DigFilterLicensed.lvlib

  Hello

  I'm trying to compile a program for my sbRIO-9632, but I got following error:

  Deployment NI_DigFilterLicensed.lvlib:dfd_Filter Signal by Signal of Coef.viNI_DigFilterLicensed.lvlib:dfd_Filter of Coef.vi loaded with errors on the target and was closed.
  LabVIEW: Unable to load the shared library LVDFD. *: NormFltH:C on the device target RT.

  This filter is not compatibel to Labview RT?

  I use RT 2009SP1, SP1 FPGA, Labview, SP1 and 3.4 OR RIO.

  Thank you very much

  Attached to the status of full deployment:

  Deployment NI_DigFilter_Design.lvlib:dfd_Group Delay_Gradient Optimization.vi (15.72 K)
  Deployment NI_DigFilter_Design.lvlib:dfd_Group Delay_Integer Tau.vi (12,93 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Specific TF Validation.vi (22,94 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_IIR filter Cluster Validation.vi (9,62 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Create filter Coef of ZPK without Attributes.vi (18.67 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Get a Quantizer.vi FXP (12,50 K)
  Deployment NI_DigFilter_FXP.lvlib:dfd_Validate Quantizer.vi (9,34 K)
  Deployment of managers NI_DigFilterLicensed.lvlib:dfd_Error .vi (multiple) (6.89 K)
  Deployment NI_DigFilter_Design.lvlib:dfd_Group Delay_Params Validation.vi (22,54 K)
  Deployment NI_DigFilter_Design.lvlib:dfd_Group Delay_Initial Guess.vi (12.65 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_TF Validation.vi (13.52 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_TF to filter the Coef.vi (37.91 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Get Filter Type Coef (filter IO) .vi (13.76 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Write filter Coefficients.vi (13,97 K)
  Deployment floating NI_DigFilterLicensed.lvlib:dfd_Build filter Coef.vi (16.68 K)
  Deployment NI_DigFilterLicensed.lvlibFD Build filter transfer Function.vi (13.02 K)
  Deployment NI_DigFilter_Design.lvlib:dfd_Group delay Build Allpass Filter.vi (11,19 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Set a Quantizer.vi FXP (12,69 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Read filter Coefficients.vi (14.07 K)
  Deployment NI_DigFilterLicensed.lvlib:dfd_Filter Signal by Signal of Coef.viNI_DigFilterLicensed.lvlib:dfd_Filter of Coef.vi loaded with errors on the target and was closed.
  LabVIEW: Unable to load the shared library LVDFD. *: NormFltH:C on the device target RT.

  Hello chefweb,

  Make sure you have installed Toolkit Digital Filter Design and it is operated properly, then follow the screenshots below in your measurement & Automation Explorer (MAX):

  

  

  

• ESXi 5: sharing 4 cores with VMs - parameters of vCPU 3

  Hey people,

  First of all, I shamefully admit that I am relatively new on ESXi and while I could probably find the answer in the plethora of documentation, I spent hours and come up with nothing.

  You are looking for a simple answer to a simple question:

  What is the best way to share also the 4 cores of the processor (4 physical cores on the host node) with 3 virtual machines?

  I know there are a lot of variables that can be introduced to the equation (type of software used, VM operating system, etc.), but I just want to give each virtual computer as the equal of a hand as possible.

  Right now I have 2 virtual machines, each with 2 vCPUs and I really like my performance but I'm seriously slot using our resources.

  I would like to add a third VM and divide the 4 hearts among the 3 VMs.

  My stomach says to give 4 vCPUs each virtual computer and let ESXi balance the load.

  Am I wrong?

  -Scott

  P.S. It's a 1230 E3 Xeon with hyperthreading disabled, so it comes with 4 logical cores, not 8.

  (1) Please HT turn on again.  Modern HT on Ivy Bridge help to 99% of the performance of the application... especially with ESXi.

  (2) If you come to give all computers virtual resources equal (say, 4 vCPUs) and don't change anything else, they will be treated equally.

• Dual Core with 2 separate processors in a Satellite A100-599! ??

  Hello

  My Satellite A100-599 is a Core 2 Duo T7100 2 .00GHz.

  In the Manager of peripheral devices, processors, I have 2 CPUs:

  Intel Core 2 CPU T5500 @ 1.66 GHZ
  Intel Core 2 CPU T7200 @ 2.00GHZ

  Is this normal? I wouldn't not two seek T7200 @ 2.00GHZ?

  Thank you.

  Hello

  This is only a bug of Vista ;)
  You n t need to install anything from the Intel page.

  Just remove the CPU entries from Device Manager and reboot the laptop.
  Then the Vista should recognize and reinstall the software and should recognize the processor correctly!

  It could be that useful ;)

  Best regards

• Need help of payment services - native Core with Cocos2dx

  I create games with cocos2dx on blackberry 10 with in shopping, I sell the virtual money in "Cash" on my game.

  I use before local mode and then I try to use the sanbox.

  I successfully download my games on the world of blackberry with account sanbox blackberry, already downloaded my game on the world of bb and digital products is valid...

  But my problem is:

  When the purchase is successful (good and good, ID etc. is valid), I don't get money "Cash" (my money does not increase on my game store).

  I have references already opened two link on cocos2dx, but I can't get the solution:

  http://supportforums.BlackBerry.com/T5/native-development/A-post-mortem-supporting-in-app-purchases-...

  http://supportforums.BlackBerry.com/T5/native-development/is-it-possible-to-use-PaymentService-with-...

  There's an idea on the code of validation when the purchase is successful? THX

  This is my code:

  CCEGLView * eglView = CCEGLView::sharedOpenGLView();
  eglView-> setFrameSize (600, 1024);

  bps_initialize();
  paymentservice_request_events (0);
  paymentservice_set_connection_mode (true);
  purchase_arguments_t * args = NULL;
  paymentservice_purchase_arguments_create (&args);)

  paymentservice_purchase_arguments_set_digital_good_id (args, "xxxxxxxx");
  paymentservice_purchase_arguments_set_digital_good_sku (args, "xxxxxxxx");
  paymentservice_purchase_arguments_set_digital_good_name (args, "100 Cash");
  paymentservice_purchase_arguments_set_metadata (args, "Purchase of the sample");
  paymentservice_purchase_arguments_set_app_name (args, "Sample game");
  paymentservice_purchase_arguments_set_app_icon (args, "http://www.rim.com/products/appworld_3col.jpg");
  paymentservice_purchase_arguments_set_vendor_content_id (args, "xxxxxxxx");
  paymentservice_purchase_arguments_set_vendor_customer_id (args, "Customer-provider-ID");
  paymentservice_purchase_arguments_set_extra_parameter (args, "extrakey1", "extraval1");
  paymentservice_purchase_arguments_set_extra_parameter (args, "extrakey2", "extraval2");
  paymentservice_purchase_arguments_set_extra_parameter (args, "extrakey3", "extraval3");

  unsigned request_id = 0;
  If (paymentservice_purchase_request_with_arguments (args)
  ! = BPS_SUCCESS) {}
  fprintf (stderr, "error: purchase requisition has not.") \n") ;
  }

  Your code is infinitely loop to read the events? The response of purchase may not be the first back, if you read you the event once after the purchase is attempted then it would make sense that the event is so lost.

  You need to code is a loop to continuously listen BPS events.

• LabVIEW FPGA failure with compiler Xlinx?

  I'm in LabVIEW FPGA 8.6 with NOR-RIO 3.0.1 (to 8.6).  When I compile a simple program, I get the notorious:

  «Error starting compile step: make sure that a compatible version of Xilinx tools is installed in the location specified in the setup of LabVIEW FPGA.»

  I checked the FPGA compile server and I ran the utility fixTlink.VI with no improvement.  This produces two identical PC, neither one having a FPGA installed card.

  Any ideas?

  After further analysis, the problem was to be in our facility in LabVIEW FPGA 8.6.   Using the correct Installer of NEITHER solved the problem.

  This thread is now resolved.

• On a Linux operating system, what tools need to developed a real-time application that communicates with FPGA?

  On a Linux operating system, what tools need to developed a real-time application communicating with FPGA?

  It is not unclear to me by reading the documentation on the website OR tools or drivers should I install on a Linux operating system in order to develop a C++ real-time application (that interact with FPGA) which will take place on a sbRIO-9651.

  Is this possible at all?

  Thank you

  Michel

  Everything works very well with an FPGA VI, compiled with LabVIEW FPGA 2015.

  1. I have installed Eclipse on CentOS 7 with cross-compiler found at this link:

  Compilers C & C++ GNU for Linux ARMv7 (Linux host) 2014

  2. I also install a debugger crossed to debug application c / c++ remotly. Once on the page go in the section "Linaro Toolchain for Cortex-A" and download the second link linux "linaro-toolchain-binary (big-endian).  The binary gdb is in there, so you must point towards him in the Eclipse debug configuration:

  Linaro Toolchain for Cortex-A

  3. I installed the linux drivers from NOR-RIO 15:

  Driver OR RIO 15.0 for Linux

  4. I was able to program an application to c / c++ opening and running a LabVIEW FPGA Bitstream in a few steps:

  Example of API Interface FPGA C OR real time Linux and Eclipse

  Michel

• 3rd generation Intel® Core™ processors with Intel® HD Graphics 4000 questions

  Dear HP sorry for my bad English, I have a problem on my laptop
  When I played or open some game or apps there make my always 100% CPU usage, which is happen, maybe because I do not want to install the latest (3rd Generation processors Intel® Core™ with Intel® HD Graphics 4000). I get a lot of lag when played a game... but my friend with the same machine than ever
  I am looking for my problem on google, but the result is empty

  My problem:

  -CPU usage * always 100% when I opened a few apps or game

  -J' do need a link to download the latest 3rd generation processors Intel Core™ with Intel® HD Graphics 4000 *.

  -If the HP have software (support for customers) like sony (vaio care). *

  I thank you very much for the reply and sorry for the bad fate

  Hi DAli99GRT,

  Thank you for your request, I will do my best to help you!

  I understand that you have a problem with the performance of your laptop. When you play certain games the CPU usage is 100%.  Looking for updates to your system.

  You can run The HP Support Assistant to help with HP updates for your laptop.

  You can also manually check from the HP drivers & downloads and captures your exact model by following the instructions.

  How can I find my model number or product number?

  Here are the documents that may be helpful. I do not know what operating system you're running, while I have provided two.

  Improving the performance of the system without adding memory (Windows 8)

  Improving the performance of the system without adding memory (Windows 7)

  If you need more assistance, can you give us your exact model and the operating system you are using.

  Results or clarification would be useful.

• More physical cores vs less with hyper-threading

  I'm sure that this has been answered before, but is it better to have more physical cores, or I can get the same performance with half of the carrots but enable hyper-threading technology?  It is of course a discussion of type AMD vs Intel...

  Thank you!

  Hi friend

  Visualize this:

  You are in a supermarket and a bonehead out a checkbook to write a check.

  You have a gallon of milk and a $5 ticket in your hand.

  The Fund puts the first transaction on hold while the old lady wrote the check and treat your transaction. You go out, it ends by the check writer.

  That's the theory behind the HT. If a thread stops, it can perform a second thread on the same kernel. But the problem is that it can only manage a thread on any cycle, so it depends on inefficiencies in executing 'slide in this teaching of the second.'

  Now, imagine that the grocery store stops take control. Efficiency is increased, the main thread has more effective, but it is less likely for this second operation to occur. If you wait longer with your milk.

  Would you rather have a cashier multitasking or more open channels? If the company is light in the store and transactions are small, the cashier multitasking could be allowed.

  But if it's Saturday afternoon, you want only to open more lanes due to heavy traffic.

  HT works well in loads of light work where the traffic is "burst" and ineffective. But if the workloads increases (and I believe that we all have more work to do on our systems than ever) so the benefits of HT begin to slip and the benefits of dedicated hearts really shines.

  Reference: really liked above the explanation I got from this thread: 4 Cores with Hyperthreading vs 8 physical cores? UC - Performance -

• maximum number of cores on esxi dell r710 with Xeon E5520 HT

  I intend to buy a dell r710.

  This system will have 2 system physics quad core and HT technology.

  Intel® Xeon® E5520 2.26 Ghz, 8 M Cache, 5.86 GT/s QPI, Turbo, HT

  It will have 8 cores with two Hyperthreaded by heart.

  The free esxi version is limited to 6 cores per socket.

  A hyperthreading is considered as a physical core for this limit under license?

  After this discussion, it seems that a HT is handled by the same esx 3 licenses and esx2, which is HT does not count against the limit of 6 basic license.

  http://communities.VMware.com/click.jspa?searchID=6367755 & ObjectType = 2 & objectid = 1238132

  Is this true?

  Hello

  It is my understanding as well. HT is not considered part of the license that you can always turn it off. Not necessarily, you cannot disable a Core.

  Best regards

  Edward L. Haletky VMware communities user moderator, VMware vExpert 2009, url = http://www.virtualizationpractice.comvirtualization practical analyst [url]
  "Now available: url = http://www.astroarch.com/wiki/index.php/VMware_Virtual_Infrastructure_Security' VMware vSphere (TM) and Virtual Infrastructure Security: securing the virtual environment ' [url]
  Also available url = http://www.astroarch.com/wiki/index.php/VMWare_ESX_Server_in_the_Enterprise"VMWare ESX Server in the enterprise" [url]
  [url =http://www.astroarch.com/wiki/index.php/Blog_Roll] SearchVMware Pro [url] | URL = http://www.astroarch.com/blog Blue Gears [url] | URL = http://www.astroarch.com/wiki/index.php/Top_Virtualization_Security_Links Top security virtualization [url] links | URL = http://www.astroarch.com/wiki/index.php/Virtualization_Security_Round_Table_Podcast Virtualization Security Table round Podcast [url]

• Only 1 CPU Core is recognized on the Satellite L650-1MC

  Hello guys, once again

  As the title says, only 1 CPU core is recognized on my L650-1MC. There an i5 480M CPU.

  http://Ark.Intel.com/products/52952/Intel-Core-i5-480M-processor-(3 m - Cache - 2_66 - GHz)

  A monitoring program called 'speccy' says:

  Intel Core i5
  Carrots 1
  NET 2
  Name Intel Core i5
  Code-named Arrandale
  Package Socket 989 rPGA
  The 32nm technology
  Specification Intel (r) Core i5 CPU M 480 @ 2.67GHz
  Family 6
  Extended family 6
  Model 5
  Model expanded 25
  Not to not 5
  Revision K0
  Instructions, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Intel 64
  Virtualization supported, enabled
  Hyperthreading is supported, enabled
  134,0 MHz bus speed
  2412,6 MHz rated Bus speed
  Base speed 2666 MHz stock
  Stock of 133 MHz Bus speed

  L1 Data Cache size 32 KB
  L1 Instructions Cache size 32 KBytes
  L2 unified Cache size 256 KB
  L3 Unified Cache Size 3072 KB
  Core 0
  Basic speed 2934,1 MHz
  Multiplier x 9.0
  133,4 MHz bus speed
  2400,7 MHz rated Bus speed
  Temperature of 52 ° C
  Thread 1
  APIC ID 0
  Thread 2
  APIC ID 1

  The task manager has two graphics and I can change to/from the "one graph per cpu and one graph, all CPUs" in the options display, although that I thought she should have 4 graphics; which is logical that the CPU has 4 wires, so should have 4 graphics.

  Any ideas? I tried msconfig and reset the number of processors, but then it resets the memory to 2 GB so I have to reset that and restart it to recognize all the 6 GB of ram. but then my cpu is a nucleus! It seems that I have a dual core cpu and 2 GB of RAM or a simple core cpu and 6 GB ram! ATM I'm on a single processor core with 6 GB of ram. I think the only thing I can do is reset the cpu in msconfig and reboot and see if it works, but then it will set the RAM to 2 GB. I 'afraid' to uncheck the CPU and RAM at the same time, incase of my laptop computer won't load at all. What do you think?

  It is not too much a problem; If I had only 2/3 GB of RAM, then it would be a problem, would be just nice to have my CPU dual core of return!

  As always, I would be really grateful for any help with it.

  Thank you for taking the time to read this.

  Hello

  You tested it with a 3rd party software called ' speccy
  Have you tested other tools like Everest Home Edition or CPU - Z?

  Strongly recommend do it and compare the results, because a single tool can provide erroneous values.

• Satellite M60: Refresh Centrino 1.73-> T2050 Dual Core CPU

  Hello world!

  I want to upgrade my CPU a Pentium M 740 (1.73) towards a T2050 Dual Core (2 x 1, 6).

  The two processors use socket 479 mPGA and a FSB of 533 Mhz.

  The M60 have the i915 and this chipset is not support two hearts. But some sources on the internet say he's working with some motherboards. It depends of the
  Reference of the manufacturer (Toshiba).

  So... it does not work?

  welcome them

  Hi mate,

  Unfortunately, it s does not not since the chipset in this specific machine is not able to manage a Dual-Core processor. A friend of mine has tried, but the didn t of the machine starts. After replacing the Dual-Core with the previous, the machine upward, but since that time the machine started to work unstable.

  We don t know yet what could be the problem, but I recommend you do not replace.

  Welcome them