FPGA loop timing and data transfer question

Hello community,

two really matter of rookie on FPGA timing loop. Attached a screenshot of the data acquisition loop I created. The different modules have different maximum sampling rates, then what will be the speed of the loop? It will adjust to the slower module, or can I use a timer loop?

It's the loop of the acquisition, but I need to treat the data as well. Currently I transmit the data to the processor loop through which fixed the length of array FXP. I guess the best would be to use a FIFO. Can you confirm this? Or I should use something else?

Thank you!

Yes, loop rate will be determined by the slowest module. If you have some really slow analog input module, you might want to put in a loop for your fast IO. You can always put calendar information in your loop to display your real rate of loop using a shift register, subtract and a number of cycles VI.

You're right - without loss of high speed data acquisition (without losing all the data points), you must use FIFOs. If worry about missing points data (i.e. only interested in current value), then the front panel indicator reading is fine.

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