FPGA block memory and Timing FIFO

Similar Questions

• Module speed FPGA, speed controller and timed loop speed

  Hello.

  I'm developing an application to acquire an analog signal at 800kS/s. Budget does not seem to be enough buy material excess spec. So I have to be very very accurate on all components. I had a look on the site and selected the following materials.

  9221 8 module capable analog channel on 800kS/s sampling. I don't know if this sampling rate indicated in the specification of the module means that it can acquire up to 800kS/s or is the device samples ADC sampling rate to which the machine don't maybe not to the criteria of Nyquist and the module can perform sampling to 1.6MS / s is necessary which I think is not available?

  9012-400 MHZ controller controller. If I put a while loop inside a VI under the RT target, it runs at 400 MHZ by default provided there is no code inside? Is so I could definitely use loop time express vi for sampling at the required level.

  What of the timed loop? I just developed a project of RT and added vi under the RT target. The timed loop default clock frequency is 1 kHz and I can't select more than 1 MHz?

  9112 chassis. Default clock 40 MHz. same rate issue which concerns the 9012 above controller.

  Kind regards

  Hi AustinCann

  If you need to acquire 800 kech. / s, then the module module-9221 will be able to do this, if you are using only 1 channel, that is.  The module using a global sample, therefore the maximum rate will be distributed on channels that you use.

  If, however, you have to detect the frequency of > 400 then you would need a higher sampling rate to detect these, as you mentioned.

  The controller processor runs at 400 MHz, even though the loops in your code will not run at this pace.  On the target in real time, you can use a timed sources of clock - usually 1 kHz to 1 MHz - and set the period in terms of the chosen clock.  If you need faster line rates, you can still code directly on the FPGA.  The CompactRIO Developers Guide is a comprensive document and deals with most of the concepts of RT and FPGA.

  The best course of action would be to contact your local office, because they have all the resources necessary for the specification of your system.

• Use of FIFO memory on two areas of clock (Labview FPGA) block

  Greetings!

  I'm developing an application on the FPGA of the vector signal OR 5644R
  transmitter/receiver. I have two loops single-cycle timed: a 40 MHz making a convolution
  and writing a FIFO memory block and the second at 120 MHz (sample clock)
  who reads from block FIFO memory and uses the following values
  interpolation...

  Under what circumstances is it permissible to use a FIFO memory block to transfer

  values of a loop from 40 MHz to a loop of 120 MHz (sample clock)?

  The reason I ask the question, it is that the compilation of my code repeatedly of not
  reported the error below:

  ERROR: HDLCompiler:69 - "/ opt/apps/NIFPGA/jobs/J9k7Gwc_WXxzSVD/Interface.vhd" line 193: is not declared.

  I share for everyone's reference, screenshots of my code which is an extension of

  sample 'Project streaming VST' given in NI5644R. A brief description of attachments is

  given below...

  1. "Top_level_FPGA_part1_modification.png": in a loop SCTL 120 MHz, a sub - vi bed FPGA

  go a block FIFO memory... In fact, the reading is actually made when entry

  "read_stream" is activated... (see details in read_from_fifo_true_case.png)

  2. "Top_level_FPGA_part2_modification.png": a 40 MHz SCTL, wherein is a subvi FPGA

  called to write the output of convolution to block FIFO memory.

  3. "target_respone_fpga_block_FIFO_modification.png": an output of a convolution filter is

  written in block FIFO memory each time that the convolution output is available...

  'ReadBlockFIFO' VI (circled in Top_level_FPGA_part1) is invoked in a 120 MHz SCTL.

  4. "read_from_fifo_false_case.png": when the input "read_stream' of this vi is false,

  data transfer memory FIFO of block to a different FIFO ('generation filter") takes

  place.

  5. "read_from_fifo_true_case.png": when the "read_stream' is set to true, the data is read in

  'Filter generation' FIFO and spent on the chain of later interpolation to the

  120 MHz SCTL...

  I hope that the attachments give enough clarity to what I'm doing... If we need

  For more information, do not hesitate to ask...

  Kind regards

  S. Raja Kumar

  Greetings!

  I think I understand the problem... The error probably occurs because a DMA FIFO

  (FPGA host) is playing at 40 MHz, and it is checked for the number of items in a loop

  120 MHz... It is not captured by the "pre-processing" by the labview FPGA, but by the Xilinx

  compilation phase synthesis tool.

  A lesson I share, is that if you observe this kind of problem, watch if there is incompatibility

  in the areas of the clock to access a FIFO...

  Kind regards

  S. Raja Kumar

• [Labview FPGA]: block of memory use Xilinx HDL integration node

  Hello

  In my project, I would be developed my own VHDL module and integrated in my project of LV FPGA with a knot of integration.

  But for an evolution of my code, I wonder if it is possible to use in my own code VHDL, Xilinx library (as a block of memory).

  Thank you.

  You can use any Xilinx IP (or IP and others) in your external code. For example, if you generate a block of memory using block memory generator you can instantiate this IP in your own VHDL.

• Only the 32 block RAMS and always showing error 3 used

  Hello

  I work on Photons counting upon arrival at DIO0. Short cut, there is a lot of data to come and I need to send it to the host as soon as possible. To do this, I used a FIFO extended target in a loop timed under unique bike and another target host FIFO taking this extended FIFO target data and send it to the host.

  According to the analysis that I did, I need FIFO to 600 000 elements Boolean deep target. This should be possible since I use an FPGA virtex-5 wx30 FPGA which has 32 (36kbits) block of RAM. However, when I increase the number of items in this requested FIFO, compiling just can't say that code does not fit into the FPGA while it shows that only 3 of the 32 RAM block have been used.

  I tried to search a lot on any restrictions on the FIFO, but I have not found.

  Please help me here earlier.

  I have attached the file VI and the sheet of newspaper of Xilinx compilation.

  There are 6 FIFOs in this project:

  The target host DMA (items I32, 1023)

  Target to host DMA (Boolean elements, 2000)

  Target to host DMA U32 (U32, 500)

  Range of target DMA write (I32, 16000)
  County of DMA scope target (Boolean elements, 108000)
  DMA County U32 brought target (U32, 500)

  There is a bug in the compiler to Xilinx that not all types of block instantiated Rams are reported.

  I did a similar discovery before.  http://forums.NI.com/T5/LabVIEW/FPGA-block-RAM-FIFO-resource-usage/m-p/2978897/highlight/true#M85572...

  Therefore, simply ignore the statistics of the compilation, they are wrong.

  Block of RAM is not addressable as 36 k x 1 bit, it has 36 bit width or width 72 bits.  This means that 1-bit, 2 bits, all the way to the top 36-bit all fill a cell block of RAM.

  Therefore, your consumption will be 600 k x 36 bit which gives much more than what you're supposed to be bit 1 x 60000 storage trequirement.

  1x600k is part of the block of 32x36k RAM (600 KB required, 1 MB free space)

  but the reality is that

  36x600k does not fit in the block of 32x36k Ram (21 MB required, 1 MB of free space).

  If you can, try little racing Booleans in one FXP 36 bits before writing in the block of RAM will improve you things.

• Coregen memory when you use defined VI block memory

  I currently have a problem when you try to compile a VI for my card Flex RIO (SMU-7965R).  I have a sub - vi which contains a small instance memory set by VI (U16 X 256 elements) and a block of DSP48.  This VI is instantiated 128 times in the top level VI.  When I set up the memory set by VI to target the block of RAM in the FPGA, the compilation process is suspended during the generation of the nuclei (memory after ~ 45 min).  LabVIEW treats each instance of as single block memory when executing coregen?  I do not experience this problem when I set up the memory set by VI using LUTs.  Any thoughts would be appreciated.

  Thank you

  Brian

  Hi Brian,.

  I believe that this compilation failure could be less related to the implementation of memory coregen, rather the memory of the way that is implemented in the lut and block memory on an FPGA. Lut are built through flip-flops and are perfect for storing information 100-300 bytes, while the memory block is segmented in a fixed size of 2 k RAM embedded. There are only a number of structures of block of RAM in a given FPGA and it seems that in your case that you use more of your resources block of allocated RAM. For example, in the 7831R if we tried to implement a FIFO in the maximum possible storage size block memory would be 81 920 bytes due to the limitation of resources.

  The implementation of flip flop of the LUTs will allow the compiler greater flexibility in the use of resources in compiling because the size of the LUT is not fixed in the way that is a block structure of RAM. This is probably the reason why this LUT implementation is compiling successfully while the RAM block is not in this case.

  Kind regards

  Blayne K

• Move from LabVIEW FPGA block of ram address to node CLIP?

  Hello

  I need to pass an index memory RAM of LabVIEW FPGA block to a CLIP node to the node CLIP to have access to the data in the BRAM.  The node of the ELEMENT contains an IP address that we developed and the IP address is the use of Xilinx BRAM driver to access data.  I guess that we need to move the physical address of the BRAM to the ELEMENT node.

  Is this possible? If so, how? If this is not the case, what would be an alternative?

  Thank you

  Michel

  If I understand you correctly, Yes, you should be able to use the memory block of the Xilinx pallet Builder in LabVIEW FPGA and in the loop of the single Cycle, connect the ports of this block signals CLIP exposed by the IP of your colleague. You may need to tweak/adapt some of the signals slightly to the LabVIEW data flow.

• My calendar retains the events for a month, but when I look back over the past months, only recurring and default events are preserved.  I have a bad memory and I want that all events held on my calendar.  How can I do this?

  My calendar keeps events a month, but when I think back several months, only recurring and default events are preserved.  I have a bad memory and want to keep all the events, I put on my calendar for a year.  How can I do this?

  Go to settings > Mail, content, timing and you should see an option for synchronization. Make sure that you put in all the events if you want to keep past events calendar

  Alternatively you can also use iCloud.com to restore calendar events that may have been accidentally deleted

  If you've accidentally deleted your calendars, reminders, or contacts of...

  I hope this helps!

• There seems to be a MAJOR problem (blocking/memory leak) in "subject: House", also known as the Firefox Start Page, at 26.0 Firefox on Windows!

  There seems to be a MAJOR problem (blocking/memory leak) in "subject: House", also known as start up Firefox, 26.0 Firefox Page, Windows!

  seen on:
  -Windows 7 x 64 machine with 12 GB of RAM and high performance CPU (core i7-920)
  -Comments Machine virtual WinXP SP3 (in Oracle VirtualBox) running on the same computer
  -Intel Atom D525 netbook with 4 GB of RAM, running Win7 x 64

  None of these machines are connected through Sync or something like that. The Firefox instance on the virtual machine is a fresh install / clean.

  The problem:
  -100% of cpu usage for 10 seconds, (util in XP) memory usage goes up to 1.7 GB
  -If "subject: House" is actually the Firefox Start Page, it blocks the computer at startup of Firefox for 10 seconds
  -If "subject: House" isn't the Firefox Start Page, startup is fine - BUT if I press the "home" on the toolbar button it loads "on: House" which causes the same question once again

  Sounds that there is a problem with one of the code snippets that are responsible. I've seen several reports on this issue.

  You can set the browser.aboutHomeSnippets.updateUrl pref an empty string on the subject: the page of config to disable loading (new) checked to see if that helps.
  
  You can open the topic: config page through the address bar

  • http://KB.mozillazine.org/about:config

  You must remove the ' storage\moz-security-about + origin "folder in the folder of Firefox to delete already profile stored clips.

  You can use this button to go to the Firefox profile folder:

  • Help > troubleshooting information > profile directory: see file (Linux: open the directory;) Mac: View in the Finder)
  • http://KB.mozillazine.org/Profile_folder_-_Firefox

• Using of FPGA VHDL IP and analog output

  I use a system with Labview 2014 PXI. I've got Labview FPGA to program and run the card PXI-7854R.

  I have the VHDL Code I want to use to control an analog output of the card. I use the IP integration node for this now but I also tried it making the process CLIP and still have not been successful. The problem that arises is that the IP integration node must be in a timed loop, while the analog output indicates that it cannot be put in a timed loop. Is there a way to provide an output of VHDL analog outputs of the card?

  I tried to embed a loop timed within a while loop, but it still does not work.

  I can't download the VI due to the policy of the company, but suppose I'm generating a sine wave in my VHDL code which must lead to the analog output of the card (the actual wave is company owner information but it is generated by a glance to the top of the table as a sine wave VHDL would be).

  In an attempt to work the problem I retried import CLIP of the HDL code in a new project in Labview and VI. I'm still not sure about why it did not work with each other when I tried it.

  For anyone who seeks to solve this problem:

  I basically used this tutorial for the process CLIP: http://www.ni.com/tutorial/7444/en/

  It also explains the differences between the CLAMP and the IP integration node.

• I use an ipad to a friend not locked... I have myself a code and a apple ID... It works well, now afete upgrade to the latest os blocked .i and wonder the old apple... what to do ID. ?

  I use an ipad to a friend not locked... I have myself a code and a apple ID... It works well, now aferupgrading in the last os blocked .i and wonder the old apple... what to do ID. ?

  Hello

  You describe Activation Lock, which prevents the unauthorized use of the iPad if it's lost or stolen.

  This can be disabled by the person who helped him either entering their Apple ID and password of the device or to remove the iPad from their list of devices to find my iPhone via iCloud.com.

  If the friend who sold or gave the iPad for you is the original owner and who has activated locking Activation, they can try to recover their Apple ID information and forgotten password if they have forgotten one or both of them:

  • If you have forgotten your Apple - Apple Support ID
  • If you forgot your Apple ID - Apple Support password

  If they cannot recover this information (and therefore can't follow the steps described above), but they still have their proof of purchase as the original owner of the iPad, ask them to accompany you and the device to a Genius Bar appointment, where Apple may be able to help by removing the lock.

  If you can not organize or any of these measures, then you will not be able to use the iPad. There is no way around this security feature.

  More information and instructions:

  Turn off find my iPhone Activation Lock - Apple Support

• I have an iMac OSX 10.8.5 2008 30.6 GHz Intel Core 2 Duo Processor with 4 GB 800 MHz DDR2 SDRAM Memory and 1 t HD

  I have an iMac 24 "Early 2008 OSX 10.8.5... 30.6 GHz processor Intel Core 2 Duo with 4 GB 800 MHz DDR2 SDRAM memory and 1 t HD.  Can I upgrade the processor speed and if so what.  Can I upgrade the memory and if so what.  I launched iPhoto ' 08 7.14.  Any input would be great.  Thanks for your help and suggestions.

  You can actually move the ram to 6 GB.

• How to take movies on my macbook air to free up memory and still access those I downloaded from iTunes?

  I want to free up the memory on my macbook air and have 65 GB of movies hogging the space. I don't want to lose them forever if you want to know how I can free up memory and again back to the film at some point in the future.

  If they were purchased through iTunes, you can download again them at any time.

  However, there is no way to stream movies, so you have to download the entire file again for a movie.

  Open iTunes > iTunes Store > purchased (on the right side of the window) > movies.

  Make sure that the sort is set to "Not in my library" If you try to redownload something that has been removed from the computer.

• I want to upgrade to El capitan, but need to 8 GB memory and now have only 4.  How much would it cost to add 4 GB of memory?

  I want to upgrade to El capitan, but need to 8 GB memory and now have only 4.  How much would it cost to add 4 GB of memory?

  It depends on what Mac model you have and is not possible for all models. Go to the website of OWC or Crucial and check.

  (141711)

• I have a macbook pro 15 "model 9.1 4 GB of memory and want to extend to 8 which is the model of memory should I buy for my fastest machine, I have for several years.

  I have a macbook pro 15 "model 9.1 4 GB of memory and want to extend to 8 which is the model of memory should I buy for my fastest machine, I have for several years.

  See:

  http://eShop.MacSales.com/shop/memory/Apple_MacBook_MacBook_Pro/upgrade/DDR3_160 0MHz_SDRAM

  Get only the memory of a place as above, since Macs are picky about the memory. Another place is crucial.

  If you can't swing for 16 GB (2 X 8 GB) replace a strip of 2 GB with a key of 8 GB.

  This is the Office Mac Pro forum. I asked that your post be moved to the MacBook Pro laptop forum.