FPGA project daily Software development management

I noticed that every day when I finished the work on the project and take a copy of this project and rename it to serve the next day and open FPGA vi in the new project file, Xilinx begins once again compiling FPGA VI. Is there a method that I could manage my daily work so the next day, I opened the FPGA VI of new folder, it will not ask for another compilation?

Kind regards

Austin

Hi Austin,.

I reproduced the problem as follows.

(1) create a folder and save a new project inside
(2) create a FPGA target in the project

(3) create a simple FPGA VI under the target
(4) create a specification to build for the FPGA and compile it.
(Note that the automatically generated name to the bitfile)

5 *) copy the folder with everything (folder project, FPGA VI, bitfile, alias, etc.) to another folder
6 *) try to run the VI freshly copied directly under the target FPGA (it will start to compile)

Reason: The name of the bitfile you specify (in the build specification) has changed to a new name that didn't exist not before, so try LabVIEW compiles again.

Here's my spec to build the original project...

Here are the specifications of the copied project...

If you replace steps 5 & 6 with 2 steps, it seems to prevent the recompilation.

5 *) copy the original file with everything in it
6 *) this time, change the name of the bitfile in build specification copied the same as the original name of bitfile (see step 4)
Run the FPGA VI and you will notice that you will not need to recompile this time.

Thanks for your time,

Tags: NI Software

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