Cannot add to the target FPGA project

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• How to use the target FPGA and co. on the same chassis cRIO?

  I have a cRIO system consisting of a master chassis 9074 with several modules IO and EtherCAT 9144 slave unit.

  I want to run a CIE (see: http://zone.ni.com/devzone/cda/epd/p/id/5333) on the chassis of the master, this uses the analytical engine. At the same time I have to do some very urgent measures if I want to use the Board in hybrid mode, using analysis and FPGA engine at the same time (as described here: http://digital.ni.com/public.nsf/allkb/0DB7FEF37C26AF85862575C400531690.)

  But as soon as I add the FPGA target at one of the chassis, the feature of the ice on this chassis stops working. After some research, I found that the CIE can initialize is no longer the modules belonging to the frame that has the target FPGA on it. Error in the method Init of the CIE is: 65700 (indeterminate). This occurs when you try to use "for a more specific class' on the modules configured with a target FPGA on it.

  Someone knows what can cause exactly this problem and perhaps provide a solution/work around?

  Many thanks in advance.

  Hybrid mode requires you to have a bitfile compiled running on the FPGA to be able to read the Scan Interface IO Variables.  Move the target FPGA at the RT target module will allow Interface of scanning for this module, but the frame will always mode Interface of LabVIEW FPGA.

  

  To get fair access to the scan mode for the frame, right click on the chassis in the project, and choose Properties.  Then, modify the Scan Interface programming.  If you want to continue using the programming of FPGA and the Scan Interface set (hybrid mode), you will need to compile a bitfile (empty if you do not want programs on the FPGA again or containing your FPGA code).  By compiling, the support of the module scan mode for the modules under your RT chassis is compiled in your custom bitfile.  Then, on your VI RT, you need to use reference FPGA VI open to your newly compiled VI.  Once this VI is deployed and ongoing implementation, you get the data from you are the CIE.

  For more information, see this knowledge base article and Reference Interface of Scan CompactRIO and procedures.

• In the target FPGA read/write control function?

  Hi people,

  I learn a lot from the sample project FPGA, including how you can easily retrieve and set controls and indicators in an FPGA using the read/write control function running in an RT target.

  However, I can't find a way to do something similar in a FPGA target.  I've been down this road before - that is, trying to move the data in/out a looping VI FPGA (void) to a (parent) FPGA VI - where my memory points to reach what I needed use.

  So I was happy to see the palette FPGA enabled me to drop the control functions to read/write on a FPGA vi target.  But alas there where tons of errors (not compatible son for target, etc.) and I guess now it's not possible.

  So, just to be sure, I'm not missing something, is there something like control functions to read/write to use in an FPGA for read/write in an another FPGA (looped)?

  In addition, why would I be able to read/write on a FPGA vi control functions if they are not supported?  (Sorry for the n00b question)

  Thank you

  Steve

  maherhome wrote:

  You're right that I don't have this knot in my palette.  However, I also do not seem to have a Refnum Occurrence in the palette is in the FPGA (see below), but I need to synchronize several loops of FPGA and added research using the textfield in the VI editor (and if compiles and runs).  So 6 months to Labview and I'm fuzzy on how the palette is restricted

  I don't know what you're trying to prove here. There is no control of refnum in search in your image. Occurrences are available in FPGA, and for control of refnum for one you just right click on a function of the instance and create a control. If you can create a valid thread of a certain type of data, then you can create a control or the indicator for it, regardless of the question to know if this type of control or indicator appears in the palettes. However, the functions that you can use in the block diagram are limited by what is available in the palettes.

  maherhome wrote:

  Regarding orders read/write for the FPGA/lights, I'm surprised that the infrastructure developed to allow read/write between RT and FPGA has not mobilized to allow read/write between FPGA and FPGA.  The elements of memory function, but they are less convenient.

  You may have noticed that you cannot compile the individual parts of an FPGA VI and combine them later; This is because when you compile an FPGA VI, all its subVIs are essentially merged to create a single block diagram (with additional logic if one not reentrant Subvi is used in multiple locations, this is why it is not recommended on FPGA). The subVIs no longer exist in the FPGA compiled; reading and writing a control on them would make no sense. If you want similar behavior, use global variables - but understand that global variables store values in FPGA logic resources. Using the elements of memory (or FIFO, which can also store in memory) leaves more fabric available FPGA logic by storing data in resources specially designed for this purpose.

• date and time of transfer to the target fpga

  Hello world

  Can I transfer the date and time of real time on target fpga in a sbRIO?

  Thank you

  Hello

  You don't know why you would want to try this, can you clarify?  You cannot send the timestamp as it is, but according to what you want to do, there will be a solution.  This describes how a timestamp is stored in LabVIEW, but you probably want to send/receive something more easy to handle on FPGA.

  Michael.

• Change the target fpga

  Hello folk of LabVIEW FPGA,

  I have a project on target FPGA X, and I ran out of resources.

  I want to recompile it on Y to the target to see if I'll be better off.

  I saw this article

  http://www.NI.com/white-paper/5075/en/

  What explains the steps required at the port of the target of the target.

  But in my case, I have multiple FIFO and registers said... I really wouldn't go well the process of re - declare them again, not manually, this could be source of errors.

  Please see screenshot for clarification on what I mean.

  So, is there advice, what a FPGA gurus you can give me to help out me?

  Is there a way that I could copy a section of the LV Proj XML or somethig so that I don't have to report again to the hand like a robot?

  Thank you

  Maciej

  so Bravo goes to a colleague of mine.

  What you can do is select all the elements (of the FIFO and registers) you want to copy.

  Go to the menu of LV Edit-> copy.

  and then go to the LV menu in the new project, select the place you want to stick to the and then edit-> paste.

  

• Cannot add to the vCenter VM inventory

  Hello.  I found the file for a virtual machine on one of our data warehouses.  I don't see the virtual machine in Virtual Center.  When I try to add to the inventory, I get the following error:

  "A virtual machine or a model having the samename is already registered.  Server error: the specified key, nam or ID already exists. »

  The vmware.log file has these entries

  07:53:06.529 May 21: vmx | Client SOCKET connection 1 closed
  07:53:06.529 May 21: vmx | vmdbPipe_Streams: cannot read

  Is there something that I am missing?  Is it possible to add the virtual machine to my inventory?  Thank you in advance for the advice and help!

  Shayne

  have you tried restarting your vCenter Server Service?

• Deploy the cRIO/FPGA project on identical targets

  All, I apologize that this seems to be a frequently asked question, but I'm wondering if anyone has the tricks in their bag.  I'm looking to create several identical parts of a tester, and I'm looking for the most effective way to have a unique (RTexe and FPGA bitfile) code base that I can deploy on a bunch of cRIO-9035.

  My best case scenario is that I can compile for a chassis and deploy for the rest, because I won't be able to support long-term material and which would minimize the possibility of errors creeping in different compilations presents (and make it easier on anyone that upgrades the equipment later).  In addition, it is about half an hour to recompile everything for a new chassis, which is just a pain.

  What think you of all?

  Thank you
  Jeff

  Use the utility of replication and deployment (RAD).  It is a tool developed by the engineers of system OR specially for this purpose.  The underlying idea is to get a working system and then you take a picture of him.  You can then deploy this image to the rest of your controllers.

• Cannot add co-owner for my project? The button does not work.

  Hello

  It seems that something is wrong with the button "+ co-coproprietaire/credit", when I press nothing happens. Also I asked a friend to check his profile and he too does not work.

  Thank you.

  Hello - please write to our official support to help.behance.net - I think that it is a known, but it is to be resolved as soon as POSSIBLE.

• Number of cycles in the target FPGA VI

  Hello to everyone.

  I'm working on a project where I use sb RIO 9636. I subtract a number of past and present of the encoder pulses. Here, I have attached VI that I use as target VI. When I use simulated I/O lets say that the program works correctly. When I compile VI on sbRIO I noticed that the LED indicator named x = y? never flashes (even if she flashes simulation).  Also, when I put indicaton on the number of cycles of control, counting starts from a few very very valuable.

  Could someone help me?

  Thanks in advance.

  Hi Chupka993,

  I suspect that part of the behavior of the that you describe, is that when you change the clock of the loop, you change the speed at which the loop works. As GerdW said, this loop timer setting gives your code a rate at which it should run. For example, defining 1ms means that your code inside this loop executes once per millisecond, or 1000 Hz. ticks would work similarly, but I think the timescale ticks of the FPGA clock which is generally 40 MHz on our devices.

  When you have the timer set to 1 millisecond loop, the code in the loop executes 1,000 times per second, and your iteration count would be 1000 times before update output, which means that your code runs a full 1000 iterations once per second. If you change the clock of the loop of 2 milliseconds, the loop will run 500 times a second sense that your 1000 iterations would take 2 seconds to run. I think that the behavior you're seeing is because the iterations are produce faster that you intend.

  You need to understand exactly how much time it should take your loop to run 1000 times and then set the timer loop to the appropriate value to achieve this goal.

• Cannot add to the MP3 download Site

  I am a real novice things Dreamweaver and tech - a writer of humor with a Web site. I learned enough it is up and running, change the content on a regular basis, etc. (it will not be won no prize design)...
  
  But I worked on a music project and I have a track ready to release into the world. So I wanted to put in simple download... saved to as an MP3 via iTunes... downloaded on my site... Then I went to the websites of others with music downloads, "given the code"... Ended it very simply use the link text, ala < a href >, which helps to establish links with the MP3 (which seems to work in other sites...)
  
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  I'm confused, but have the idea that I'm missing something here and something quite simple...

  As I said, try the RAW DATA.

  And check out this reference: http://www.personal.psu.edu/wrc2/macftp.html

  O'Chief says:
  > I have never used DW as an ftp server... I can look into the issue. Although the
  > Binary mac II granted the ferry, most of the files I download simply as "text".
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  > don't be...
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  > I will look into those things that I can - have to pay attention to
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  > had on my system

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  In our environment of Esxi 5.0 U2, on a single physical host of Esxi, I created two virtual machines to Win 2008R2, I don't have any MSCS cluster. I created a LUN and presented to the host, the size of the logical unit number is 10 GB. I've added it to VM1 as RDM (virtual) and it is perfectly correct, I'm able to see in windows. When I tried the same add RDM of VM2, I found the choice of the RDM is grayed out, why is, it is not possible to allow 2 virtual machines see same RDM?

  I've attached screenshots to understand how it looks. The SCSI bus sharing on VM_1, I chose virtual to share a "vdisk" between VMS in same host, but that did not help either, I realized later, it is to share a "vdisk" and I'm looking for using RDM even in two VM

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