FPGA time off sistematically

Hello

I use 2 targets to host FIFOs DMA to transfer data acquired to the PC host (see photo).

In the FPGA vi, whitin the while loop, I use a wait (in microseconds).

Regardless of the "dt" given this expectation, in the home value I remember in time data with a systematic error:

each 10 points, the time elapsed is not dt but (dt + 1 microsec).

A small mistake, it becomes significant when dt should fall below 10, because I need and complicates the analysis.

This behavior is always the same, not random (I get 10 good 'dt', then a dt + 1 microsec, and vice versa).

I wonder if I did something wrong or if it's a problem.

Thank you

You should try using a Structure of sequence:

By the help documents:

To manage delivery rates with the Express VI loop Timer, set loop Timer Express VI in the first image of a flat sequence or stacked Sequence structure and put the rest of the code in the following frames.

EDIT:

You should also note that the first iteration may be turned off.  There is nothing that can be done about it (from what I understand).  But after the first loop, each execution else will follow very strictly to your timing chosen by the VI Express loop Timer.

Tags: NI Software

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