Hardware implementation of the controller DMA using the FPGA and LABVIEW

Similar Questions

• What is the use of FPGAS and how it differs from the IO Modules

  Hi all

  Maybe it's a silly question for most of you.  But I have very less knowledge about the basic concepts of electronic (FPGA, real-time) to cRIOs. I know that FPGA

  can be used to generate circuits within the chip that helps by some logical functions.

  I've just started working in the cRIO.  My question is that we have Modules e/s making it outputs all the application entry.  So, what is the purpose of e/s in the FPGA.

  Lets consider that we entered for an application of RTD.  In this case the module NI 9217 itself exits 24 bits of data from the RTD measurement which may be the process of the LabVIEW VI.  What will be this FPGA between the i/o Modules and the processor will help in?  Also I want to know what type of communication is used to send data between the FPGA and host modules.

  Thanks in advance

  Ajay HI:

  Sorry, you do not have an answer to your original question. However, you are right about the benefits of the FPGA. You said, if you build pre-processing in the FPGA, you can unload a lot of potentially CPU calculations out of the host processor. In addition, the program running on the FPGA is highly deterministic and can run the code very quickly. So if you build a kind of guard or evanescent dog part of your application, the FPGA is a good place to put it.

  To answer your other questions, communication between the modules and the FPGA is generally above the SPI and the data can be transferred between the FPGA and host via DMA FIFO operating on the PCI bus or single point save access using read/write in the FPGA host Interface controls. You can also use interruptions in signal of disputes between the FPGA host.

  I hope this helps, but let us know if you have any other questions.

• What are the differences between LabVIEW and LabVIEW FPGA and LabVIEW RT

  I need a comparison of LabVIEW, LabVIEW FPGA, and LabVIEW RT

  Sorry, I misunderstood.

  LabVIEW RT (LabVIEW Real-time) combines graphical LabVIEW of programming with the power of a real-time operating system, allowing you to create applications in real time.

• Implement and control 'meter' in S7 - 300 by the OPC and LabVIEW

  Hello world

  I use a S7-300 PLC and OPC Server for my projects. I have a problem: S7 - 300 has a meter module which digital signal of County. I only can implemented using SIMATIC STEP 7. Can I set up the meter module using only the server OPC and LabVIEW

  does anyone have a solution or an idea for my problem?

  could you please help me...

  Thank you

  Hi Echion,

  NOR-DAQ (MX) is used only for material OR: no you can not use it.

  To program the controller you must use the right programming environment. For Siemens S7, you need to use Simatic (or perhaps some other 3rd party software supporting IEC61131). Point.

  The OPC server is used only for the exchange of data. This is no interface programming!

• Number of DMA FIFO of items to read mismatch in the FPGA and RT

  Hi all

  I use myRIO, LV14 to run my application.

  Request: I have to continuously acquire data via FPGA and host RT process once every 2000 samples are taken. I use DMA FIFO (size 8191) to acquire data, use timeout property in the FPGA to eliminate the buffer overflow. I had followed cRIOdevguide to implement this part. An excerpt of what I put in place is attached. All code runs in the SCTL at 50 MHz.

  Question: Two or three times I met with this strange behavior, the FPGA FIFO gives continous timeout and the RT is unable to read the FIFO. The number of elements to set the property in the FPGA VI gives 0 showing that FIFO is full and no more can be written, but the RT, remaining items gives 0, so it is reading 0 (none) elements.

  Solution: I put a case where I'll write to FIFO (under the code) and if the number of elements to write is different from zero. It seems to work fine, from now.

  What confuses me, is that my FPGA VI said that FIFO is full (number of items to write 0 = FIFO) and gives a timeout error, but RT VI said that number of items remaining in the FIFO is 0 and therefore no data is read. No idea why this is so? My RT and FPGA VIs continues to run, but with no gains or to read data.

  A few minutes after you run the code, I've seen this behavior. No idea why this happens? I try to reproduce the behavior, and will update if I meet with her again. Sorry, I can't post my code here, but I guess the code snippets to explain some extend.

  Thank you

  Arya

  Edit: Even with the mentioned workaround solution, the problem persists, now that the FPGA written any of FIFO. And the RT VI is not able to read all the elements he sees 0 items in the FIFO. The FIFO continues to be in a State of timeout. So I guess that the problem is on the side of RT.

  Why it looks like you read from the FIFO even in two different places in the same VI, at the same time? If the lower reading throws the FIFO, it will never trigger the reset, which could lead to the situation you describe, I think (it's hard to tell from a few screenshots).

  Also, your logic seems too complicated. I immediately noticed that there is no reason to select the entry, the output of = 0 - simply use the 'equal to zero' output directly. On the side of FPGA, why you need check the number of items that you want to write? There's nothing wrong with writing in a FIFO that is already full. just the data won't get written.

• implementation of the 'left' and 'Right' with a GraphicElement Custom

  Hi, I expanded the GraphicElement class to create a spark dynamic star (in fact I extended the 'FilledElement' which subclass GraphicElement).

  I got the draw feature to work properly, it is implemented pretty much the same way, it would implement a spark rect or primitive ellipse, except using a RADIUS outside and inside rather than the width and the height. And that is the problem:

  When I put the left, right, up, down, width, or height properties, they are ignored. I guess that there are more functions that I need to replace to create this feature and hope to collect a vision a bit.

  Ellipse both Rect substitute the following protected functions

  transformWidthForLayout ( width: Number, height: Number, postLayoutTransform:Boolean = real ): number

  transformHeightForLayout (width: Number, height: Number, postLayoutTransform:Boolean = true): number

  getBoundsXAtSize (width: Number, height: Number, postLayoutTransform:Boolean = true): number

  getBoundsYAtSize (width: Number, height: Number, postLayoutTransform:Boolean = real ): number

  getLayoutBoundsX (postLayoutTransform:Boolean = true): number

  getLayoutBoundsY (postLayoutTransform:Boolean = true): number

  In addition to the draw (g:Graphics): Sub.

  What is my element missing to enable the features of traditional provision?

  and if so, someone please provided a vision a bit on the objectives of these functions? the reference library is pretty vague.

  Thanks in advance,

  Jenn1ngs

  Yes, I think that you will find in the Center, do the math to determine the distance to

  the edges of the area encompassing and go from there.

• Need assistant in a few concepts of as the implementation of the FIFO and comparing and front panel

  Hello

  Which attached VI made the series and convert Hex byte and then store them in the file. It should look like:

  53

  00

  01

  FF

  00

  FF

  00

  FF

  00

  I am trting to do is make a FIFO and compare it with the other having the condition of termination required... is problem in implementation, not to get a good way to do...

  try to make it a condition for the end of the data model in the next data as "FF00FF00FF00" when every I get this continuous data loop should end. Sending you vi also with details marked in...

  waiting for your answer...

  Hi Ali,

  See attachment: hex was created formatted your entry without inclusion of characters at the end...

• synchronize the microcontroller and labview Visa series

  Hello

  I have a small problem with my labVIEW VI. I do the following things:

  1. I send 7 features of the microcontroller to Labview under string (ASCII characters) to a time interval of 31.45mS.
  2. In labview, I read the string with a delay of 32 Ms.
  3. I extracted the individual string data and then get the substring.
  4. I use the string number Converter to convert the number.
  5. Finally, I display data.

  The problem I have is that when bytes (with the Node property) is less than 4000, the reading of the data to be perfect. But once that the port reached 4000 bytes, the data I receive periodic zeros. I think the problem is with the timing of the sending of the microcontroller with the LabView data. I don't know what to do with it. Could someone advise me please to his subject?

  Thanks in advance

  Concerning

  You are only reading 49 bytes at a time.  You tell me that your buffer is longer than 4000 bytes?  That tells me you have a synchronization problem.

  If you get always 49 bytes per message, then just read 49 bytes.  Get rid of the delay and the bytes of the Port.  They are usless.  And since you also use a stop character, which makes them even more useless.  The VISA Read wait upwards for the time-out period to the number of bytes that you said that it a termination character is not received.  If you use a character from endpoint really, I had even put the bytes to read something totally outrageous, like 500.

• Transmission of data to the host of RT to the FPGA via DMA FIFO

  Hello

  I try to write data from a host of RT on target FPGA using DMA FIFO and then process these data and read then return of the FPGA target to the host of the CR through an another DMA FIFO. I'm working on the NI SMU chassis 1062 q, with the built-in NI SMU-8130 RT controller and target FPGA NI SMU-7965R.

  The problem I face is that I want to send three different tables, two of the same size and the third with different size, and I need one more small to be sent first to the FPGA. I tried to use encode dish with two executives in the FPGA VI. In the first image, I read and write the first table in a while loop which is finite (that is, a finite number of iterations). The second frame contains the process of reading and writing the second two tables (of the same size) in a while loop that can be finite or infinite (depending on a control). The problem is that it does not work. 2 arrays are displayed on the front panel of the RT VI host and works well, however, the table that should have been read in the first sequence does not appear on the front panel of the RT VI host. It is not sensible because if it is not passed from the host to the fpga and vice versa then the second image should not have been executed. Note that I'm wiring (-1) for the time-out period to block the while loop iterations until the passage of each item is completed. So the first while loop has only 3 iterations. Could someone help me undersdtand why this happens and how to fix this?

  I enclose a picture of the host and the fpga vi.

  Thank you.

  If you vote for my idea here and it is implemented, you can even omit the loop FOR fully.

  (I also propose the RE / IM divided inside the loop FOR and perform operations on complex table before the loop the transpose and reshape .) In this way, you only need one instance of these operations. You might even save some unnecessary allocations table in this way)

• Is it possible to use EAS to manage the planning of the Dimensions and the members?

  Our Organization is still under implementation of the planning and implementation partner said that you can not use EAS change members because it would cause problems and I want someone to verify this, because I have little hard to believe.  I mean, using workspace is so awkward to edit members while eas is much easier and really tempting for me to try, I don't want to screw up anything.

  Any input is greatly appreciated,

  Bret

  Yes. It is not best to use EAS to change members / any changes to metadata

  Planning is as a web based tool for planning/preparation of the budget having Essbase as a backend database and all the metadata is stored in a repository of the relationship (of planning) and are pushed into Essbase (where your data is stored).

  If you use Web Forms / has all the planning, and if you make changes to members directly in environmental assessments, it is reflected in planning and it is always advisable to not make changes directly from EAS.

  If it's just one / two Member changes then I would directly in the planning of the workspace. If there is a set of members then I prepare a file and then run it using contour load utility

  HTH

  Amarnath

  ORACLE | Essbase

• Broken the FPGA VI but the empty error list

  Hello!

  I'm trying to run a vi which includes a 'Open FPGA VI Référence' function. However, an error and it says that "not compiled FPGA VI. When I try to compile the FPGA VI a message saying "The VI is broken". I try to run the FPGA and when appears in the error list, there is no error or warning in the list, although the name on the fpga includes the Red 'X' ('show warnings' is checked). Any help?

  I'm using Labview 2013.

  Pablo

  Hi Pablo.

  Sorry for my delay in responding, you managed to get the respected FPGA.vi yet?

  To answer your questions, if the project is ok with an empty FPGA.vi, then in theory, your hardware is configured ok. However, due to the vi being blank, you haven't tried to use one of the modules on your system, so it can introduce errors. The most common mistake is differentiation of mode Scan Mode/FPGA by installing the project in the first place. Also be aware that not all FPGA targets supports everything, for example some dislike for the rows that have an index to calculate the number of iterations, rather than a constant wired at the entrance to "n".

  Out of curiosity, why you place every measure in the DMA separately and also specify address? Is there a reason you don't just place all the measures in a table and put everything in the DMA, then divide the table on the other side?

  Generally speaking I don't think that incorrect programming should never cause LabVIEW crashing and you should always report the problem to the OR in order to take a look and see if they can fix it.

  Hope that you managed to get your problem sorted and again sorry for the late reply.

  Darren.

• How to set up the schema and users?

  Hello

  I'm looking for the best option for the implementation of the user and the schema in my used Oracle instance only for reports. Version using Ora11g.

  Background-

  Oracle Ora-Ainstance, is the live OLTP system.

  Oracle Ora-B instance will be the new system of reporting , I am building this new system as a reporting instance. My question is how to set up users and safety for installation below?

  Planned - approach

  Instance Ora - has, some subsets of data is moved to instance Ora-Bnight batch. Using the dblink, I'll be the data.

  Required users on Ora-B.

  1) ETLUser. -Will extract the data instance Ora-A and load B Orapending.  (User charges/written in the tables only)

  2) ReportViewer - read only access on the tables in the instance of Ora-B, for the generation of reports. (User reads only the data in the tables)

  You want all report data in a new scheme called 'Report', in the basis of the declaration.

  So, how I setup user and schema?

  Thank you

  Krishna

  Unless you are using versions of the previous decade and material, I do not recommend a separate database.  Material and modern versions run mixed workloads much better that the older systems were, so the need for a statement of the separate databases is dwindling.  The current trend in the industry is to CONSOLIDATE, less material treatment and bodies less.

  This has the additional advantage that your refreshes need not go on the network - you get faster performance of refreshment.  They share a buffer cache, so you can get the benefits of data already in memory.  If you are concerned about the damning reports of the treatment, the resource manager may set limits as needed.

  Your planned approach to ETLUSER and REPORTVIEWER is solid - good separation of responsibilities.  I would just create these ORA - a, the size of the SGA and CANCEL accordingly and allocate storage, assuming that the hardware supports the need for capacity.

  Users and schemas are almost synonymous concepts in Oracle.  They are separated in other platforms to database (such as SQL Server).  In Oracle, when you create a user, you have created a pattern.

• Darkness of 8.4 (1) vpn L2L filter ASA when you specify the Protocol and port

  Hi all - I've spent many hours trying to diagnose this and have read several discussions and the Cisco docs unsuccessfully...

  Situation: two sites running Cisco ASA 5520 on 8.4 (1) with L2L IPsec on the public internet between each of them. The configuration of IPsec and associated routing works as it should and we are able to pass traffic between networks private behind each device as expected. The problem occurs when you try to block sessions using a vpn-filter group policy configuration.

  Each site has 3 private subnets that are able to communicate correctly without the vpn-filter configuration. We want to restrict access to specific protocols, hosts, and ports between each network.

  SITE A: 10.10.0.0/18, 10.10.64.0/18, 10.10.128.0/18

  SITE B: 10.20.0.0/18, 10.20.64.0/18, 10.20.128.0/18

  When we apply a filter-vpn configuration which restricted access only two guests, as follows...

  SITE A: vpn_acl_x_x_x_x list extended access permit ip host 10.20.0.1 host 10.10.0.1

  SITE b: the ip host 10.10.0.1 allowed extended access list vpn_acl_x_x_x_x host 10.20.0.1

  ... the configuration works correctly. However, when we try to lock the configuration more far and specify the protocols and ports, as follows...

  SITE A: vpn_acl_x_x_x_x list extended access permit tcp host 10.20.0.1 host 10.10.0.1 eq 22

  SITE b: vpn_acl_x_x_x_x to the list of access permit tcp host 10.10.0.1 host 10.20.0.1 eq 22

  ... and then try to establish a SSH connection between 10.10.0.1 and 10.20.0.1 or vice versa, the package is stopped on the side of the SOURCE. ..

  Mar 22 11:58:01 x.x.x.x 22 March 2011 14:34:56: % ASA-4-106103: vpn_acl_x_x_x_x of the access list refused tcp to the user "" inside-data/10.10.0.1(59112)-> outside-iptrans/10.20.0.1(22) hit - cnt 1 first success [0xd8d1c1b4, 0 x 0]

  I would really appreciate it if someone could shed some light on what is wrong with this Setup.

  SOLUTION
  

  The ACE must be implemented on the source and the end of the tunnel destination to facilitate this configuration.

  EXAMPLE 1: allow SSH two-way communication between hosts on each network (SITE A can connect to SITE B, SITE B can connect to SITE A)...

  SITE A:
  access-list vpn_acl_x_x_x_x extended permit tcp host 10.20.0.1 host 10.10.0.1 eq 22
  access-list vpn_acl_x_x_x_x extended permit tcp host 10.20.0.1 eq 22 host 10.10.0.1
  SITE B:
  access-list vpn_acl_x_x_x_x extended permit tcp host 10.10.0.1 host 10.20.0.1 eq 22
  access-list vpn_acl_x_x_x_x extended permit tcp host 10.10.0.1 eq 22 host 10.20.0.1
  

  EXAMPLE 2: allow communication one-way SSH between hosts on each network (SITE A can connect to SITE B, SITE B is unable to connect to SITE A)...

  SITE A:
  access-list vpn_acl_x_x_x_x extended permit tcp host 10.20.0.1 eq 22 host 10.10.0.1
  SITE B:
  access-list vpn_acl_x_x_x_x extended permit tcp host 10.10.0.1 host 10.20.0.1 eq 22
  

  Very good and thank you for this post. Please kindly marks the message as answered while others may learn from your post. I think that you have started a very good discussion on vpn-filter for tunnel L2L.

• Paths of the application and the Plugin (32 vs 64 Windows)

  I'm working on a version of our installer of plugin to put the plugin for 32-bit windows in the folder plugins Photoshop 32 bit and the 64-bit plugin in the plugins Photoshop 64-bit folder.

  Currently our only 32-bit Installer uses the Windows registry to locate plugins directory.  (HKEY_LOCAL_MACHINE/SOFTWARE/ADOBE)

  Looking here now I see that even if I chose the two 64 CS5 and CS5 - 32 when I installed Photoshop, there is always only one entry in the path of plugins.  But there are two separate files of plugins.

  Even worse Adobe seems to have changed the Organization over time.

  For CS4, both versions are in the "Program Files" directory

  For CS5 Photoshop 32-bit directory is 'program (x 86) '.

  By changing the installation program to support 32 & 64, I would like to know the best practice to find these plugin files, so I can verify their existence (since it is possible to install only 32 or 64 rather than two) and then put the plugin just in the right place.

  Now this is pretty cool:

  get plugins path of the registry

  install

  I hope I don't have to implement of the trials and errors, such as:

  start in plugins path of the registry

  go up a level and look for other files from photoshop

  go up to another level and see if there are other program files folders

  recurse in their search for Photoshop files

  If there is no better way, the absence of a second registry entry should be considered a bug?

  Adobe has not modified the Organization of the registry, Windows did.

  I also write installers for my business, so I'm quite familiar with that.

  On 64-bit Windows, the registry path you see when you get the keys in HKEY_LOCAL_MACHINE/SOFTWARE/ADOBE are 64-bit values if you call the Registry API from a 64-bit process. They are 32-bit values if you call the API to register a 32-bit process.

  So, you can either write separate 32 and 64 bit installers, or you can get acquainted intimately with registry redirection which runs on 64-bit windows. (None of this is a concern on 32 bit only for Windows systems)

  To learn more about the registry redirection, go here:

  http://msdn.Microsoft.com/en-us/library/aa384232 (v = vs. 85) .aspx

  This is a very important page for editors of the installer to read:

  http://msdn.Microsoft.com/en-us/library/aa384129 (v = vs. 85) .aspx

• Error-63101 when executing the FPGA Interface C API Generator in LabVIEW 2012

  I'm using LabWindows CVI 2012 and 2012 LabVIEW FPGA module.  I try to use the FPGA Interface C API generator and I get the following error from a freshly generated .lvbitx bitfile.  I use the local server compiles on my PC.

  Error-63101

  NOR-RIO: A valid .lvbitx bitfile is required. If you are using a valid .lvbitx bitfile, the bitfile maybe isn't compatible with the software you use. Determine which version of LabVIEW was used to make the bitfile, upgrade your software to this version or later, and then try again.

  The problem occurs when executing CVI or LabVIEW.  I was able to do this earlier when I was compiling the FPGA in LabVIEW with the API generator 2011 downloaded from the Web site.

  A bit of weirdness in my setup, it's that I charged it off downloads from the website (latest files after 2012 NIWeek) rather than the normal distribution DVD.  I installed LabVIEW, so NI RIO, then the Xilinx tools compatible with 2012.  It works very well when you talk to the FPGA to a LabVIEW vi running on my Windows PC to the host.

  Any suggestions?

  Problem solved.  I had to download FPGA Interface C API generator 12.0.  It works now.

  I would have thought that if a product was called on the menu in LabVIEW 2012, it would be prompted to upgrade to a compatible version, when I installed LabVIEW.  The old version is not compatible with version 3.0 bitfiles, as identified on the following lines at the top of the .lvbitx file:

  
  
   3.0