logic gates

Similar Questions

• Button as a switch with logic gates.

  Hello, I am a student using LabVIEW 2012 as a FRC competitor, and I have a question/request to anyone who wants to.

  I can't find a non-buggy solution to get a button to work exactly like a switch. Either the solution train, or doesn't connect.

  I tried D type Flip Flop of all kinds, and! Q can not connect to D in LabVIEW (LabVIEW pulls the errors of "more than one data source", so a lot of logic functions that is available with other solutions, do not work on LabVIEW)

  NAND gate-types have been so tried, no dice.

  So if someone would like to help me, that's what I'm looking for:

  When the button is clicked, it sends a real constant function until the button is clicked again.

  -I can't use anything that messes with functions if the button is pressed.

  -J' I just need a simple on/off switch, nothing that goes 'around' from what currently exists and actually a buggy solution. It should be a kind of good way to do it.

  -An attachment of a VI would be nice, and what goes where.

  Thank you

  
  

• Multisin - converter Logic crashes when the generation of logic gates

  I just bought the student Multisim 13.0 for the school version and have applied the patches available for a Subscriber.  When I try to create a logic circuit logic converter, the program crashes. I'm not a Subscriber so I am not eligible for technical support. I am running windows 10. Y at - it a fix for this problem?

  Thanks for the replies. I was able to talk to tech support, and the solution was to run the program in 8 compatibility mode windows. I use windows 10.

• Application of logic gates on digital data... How does it work?

  Hello

  While working with labview, I tried to apply or digital data, he agreed the entry and responded to the output form digital too.

  I did not understand how is - this work on a digital data when entering are supposed to be Boolean for the logical entry doors.

  The outputs are also out of the assumption to 5 | 4 gives results 5.

  Also, I am attaching my VI.

  Please inform what is the logic behind this calculation.

  Concerning

  Hello

  logical operations operate with integers (any will do) too. The integer is used at the level of the ILO...

  The outputs are also out of the assumption to 5 | 4 gives results 5.

  5 is "0101" in binary representation, 4 is "0100":

  0101 OR
  0100
  ____
  0101 result
  

• Need help to create a BCD to 7-segment decoder using logic gates

  I guess I'm a bit puzzled here.  I am creating a decoder 7 segments with AND, NOT and OR the doors, but I seem to have a bit of luck to get the display of numbers 1, 4 and 9 to work.

  Any help would be appreciated, thanks.

  Spent a little more time before you look at this link:

  http://circuitscan.homestead.com/files/digelec/bcdto7seg.htm

• Digital logic design

  Hello

  I'm new to Labview. I do a thesis project that simulate IC 74LS112, 74LS90, etc... First, to simulate the meter of the Decade (74LS90), I created JK flip flop (74LS112) who use several logic gates. Then I used JK - FF to build 74LS90 according to data sheet of the manufacturers, but it did not work. After searching on the forum, I know that I can not design these IC using multiple logic gates because of bugs or something I don't know. So I need another way to complete my project. Does anyone have any suggestions or ideas? I am stuck and don't know where to start. Thank you.

  
  

• AND and NAND gate don't work well when used with 74LS193N

  When I use AND or NAND to work with 74LS193N, that it has not produced the result that I expected. Please see my download folder. I use AND and NAND gate to switch my FF JK when my 74LS193N give a 1001 signal but my FF JK switch before that when my 74LS193N produce a 1000 signal then it then it switches again when the 47LS193N product 1001. According to my observation he just to produce the signal in a very short time, this signal is able to pass through the NAND and AND farm at triggle my JK FF. I know this sholdn can't be happen. I thought that the signal that I spend when both inputs are high, I tried and NAND with any other logic gates so far its fine, so I don't have this problem hope someone can help me. For this reason all my work unable to design, it bothers me a lot...  Help!

  I guess I'm confused as to why you would use a generic part instead of parts 74LS00/08.  What you see are the differences in sync settings.   If you double-click on the door AND generic and press to edit the template, you will see the rise and fall of delay is 1nS.  If you place a 74LS08D and do the same thing, the delay of climb is 15nS and fall time is 20nS.   More likely, there is a setting of high spice for the counter where the QD line passes for a very small amount of time while the QA, QB, and lines QC transition from high to low.  The real AND doors NAND can't see this transition delays inherent in the real part spread (rise and fall).  If you change the values of the generic parts to that of the actual element values, the circuit should work.

• Digital electronics FPGA Board Hardware Driver for Windows 10

  My son just made me aware that his school has a dozen of National Instruments Digital Electronics FPGA boards, but they have never been able to get them to work or actually use them in the curriculum. It seems that he has left his instructor know that I worked with FPGA Xilinx for more than 10 years and now everyone counting on me to get these maps work. The issue seems to be the USB driver. According to the manual, I tried DEFB2012_5_2.exe which simply refused to run on this machine Win 10 x 64. DEFB_4_3.exe ran, but complained that LabView components have not been installed and that it would not continue. Could someone tell me please how to install USB driver ONLY so that we can download files of bits with IMPACT? In terms of a school budget, the investment they have in these maps is not negligible. Thank you.

  Hello Dave and TGregor,

  I hope I can clear some things here. I'm sorry that you run in so many questions with your boards OF FPGA.

  First of all, direct responses:

  The LabVIEW FPGA 2015 driver should install the components needed to use the Board with Xilinx tools on WINDOWS 7, it will not work on any system more recent that the pilot has been developed before the release of Windows 8 and 10.

  http://www.NI.com/download/NI-Digital-Electronics-FPGA-Board-driver-software-2015/5857/en/

  My recommendation for Windows 8 or 10 is rather install Xilinx ISE you find on Xilinx website or on the downloads page OR:

  https://www.Xilinx.com/products/design-tools/ISE-design-suite.html

  http://www.NI.com/download/LabVIEW-FPGA-Module-2016/6231/en/

  The difficulty that you face here is that tool Xilinx ISE is officially supported only on Windows 7 and below. So even though I think it will work (and it will move to the difference in the link of the above driver OF FPGA) for Windows 8 and 10, you can continue to deal with certain issues.

  Now you are all looking to program the FPGA using an HDL, Multisim and LabVIEW? If you just use an HDL, you should be all set to go and in the dev environment, you had planned using the program. Circuit design of Multisim 'S simulation tool which includes a complete library of graphic digital components. A digital circuit can be built using the graphical logic gates in Multisim then downloaded directly on the FPGA without first having to learn VHDL or Verilog. It is quite popular among the logical classes digital introduction and we can help you by establishes that as well if you are interested.

  For anyone else who might stumble upon this page, I want to make sure you are all aware that, while the Board of Directors OF FPGA is still supported and sold, it has been developed a number of years and has recently been replaced by the Council for development of the digital system (DSDB)that uses a 7020 architecting and has much periphrials more to the program than the FPGA OF. So I know that it is not useful for the current issue, but anyone looking for if they would like to buy more OF FPGA boards, I recommend watching the DSDB instead.

  Thank you!

• Transient analysis fails: Timestep too small

  I use Multisim 10.1 to assemble logic gates of transistors for an undergrad Electrical engineering class. Part of the specification is that doors should drive a 1 or 8 pF capacitor at the output in the 1nsec voltage. (I think that the circuit, which I've made available is the version 8pF).

  "Circuits work very well when I test for logical functionality with a frequency of input measured in seconds, but when I try to measure the time of release of a Ghz entry, the transient analysis invariably fails with a ' no time too small" error.

  I looked through the site or all kinds of possible fixes (adjustment of the values of the relative and absolute error, etc...), but no luck.

  for example, the project in question are: http://dl.dropbox.com/u/4286123/callforhelp.zip

  I would appreciate any advice, anyone can give me to help get the circuit able to run a transient analysis of higher frequency.

  Thank you!

  Brian Lojeck

  Student in EE, CSULB

  Hi Brian,.

  I took a glance at your circuit and it seemed that your cmos_andx8_timing_test_circuit.ms10 file generates errors of convergence. I did the following two changes in the settings of your transient simulation and circuit simulated very well:

  1. Scan options > SPICE Options > Use Defaults Multisim
  2. Crawl settings > settings > no time maximum (TMAX) = 1e-13 s

  As a general rule, you want to set the TMAX parameter to be substantially less than the smallest feature of your signal. In your case, the smaller is the rise in V1 (1ps) time. If possible, try to simulate with slower rise/fall times and slew rates. It is much easier for Multisim to converge semiconductor solutions if these settings were larger. I guess you do not have the luxury here, but if you were to just test the behavior of your circuit, it would be desirable.

  Hope that helped.

• 6008 USB running random resets

  Hi all

  We use the USB-6008 to control both engines and acquire data from a number of motion sensors. We are the control with LabVIEW 2010 on Windows 7 on a laptop. Usually, it works fine, but sometimes without reason, that we can see the resets USB-6008, causing a REAL output on all channels, causing the engines whir round and round up to the stop.

  It happened one time three times in one day and then didn't happen last week. It happened once when the sensors were activated and sometimes not.

  Someone has any idea how to prevent this, or if not how can I check this software and stop it if it happens?

  Thank you

  Danielle

  6008 are fine for a control, as long as the appropriate security measures are implemented.

  Yes, they can reset from time to time... or if windows feels like it... or, if windows crashes, or apply an update, and restart the machine... all kinds of reasons.

  And Yes, all the digital outputs get pulled high when this reset occurs.  Analog output goes to 1V, you can use a comparator and a few logic gates to drive outputs digital to a "safe" State for your application, then turn them digital outputs by driving the analog output to 5V.

  A more elegant solution, as crossrulz says, use a more compatible device like cRIO or PXI controller.  Obviously, this adds considerable cost to a system.

  Power savings options are usually the culprit.  Only turn on each device and root hubs.

  

  You drive the 6008 via a USB hub, or directly to the output of the PC?  Is the PC restart or throw errors (see the system event logs)?

• boolien use of case selection switches

  Hi all

  I want to use the switches of boolien for the selection of cases in triggered mode. I mean I have a 4 switches (like lock mode when you press the trigger) when I pressed and released the button a case corresponding to the switch to be executed, but the structure of the case is able to work only with simple switches and selectors ring (but not with combinations of different States). I tried with Combinatorial logic gates, but it increases the complexity nothing else.

  some body help me to do so.

  You can use the Boolean value like this

• Toggle multiple checkboxes with a button

  I have a system that is controlled by several checkboxes. When the system has increased, the number of checkboxes has increased and now its difficult to use.

  To improve usability, I want to add "Select all" and "select None" buttons on a momentary switch and then power toggle the check boxes normally. "." So if I wanted just the number 2 box, but had others already selected, I can simply press "Select None" and then switch to #2 as usual. And if after that I wanted everything but #4, I could hit "Select all" and then switch to offshore #4. Basically, the Super 2 toggles cannot be a State they are in it overrides the control box - they have to change the values instantly. It should also display properly on the box.

  First thing I tried was using a while loop and registry change to control the property node Value [value and value (signalling)], and it all works when the condition must be true, then it should be false he quickly of impulses. I'm not sure why he does.
  I also built a system around a latch of logic gate to fight Super Select in the toggles stumble the set/RESET button according to the current state, but its strong intensity of clumsy resources, for what he does and not easily extensible somehow.

  There's probably an easier way to do this? I have attached a picture of the method of the loop-and-register (showing only a boolean, for simplicity) and included an example usage below in the cases where my explanation is lacking.

  Thanks in advance

  As a usage example, say you have three checkboxes some already toggled on:
  [1]
  [0]
  [0]
  After Clicking "Select All":
  [1]
  [1]
  [1]
  After which I want to be able to control them as normal, so I could toggle the second check box as normal:
  [1]
  [0]
  [1]
  And then click "Select All" again:
  [1]
  [1]
  [1]
  

  Use a Structure of the event.  When the button is pressed (value change event), use a local variable to set the values in the boxes.

• How do control no datafound?

  Hi all
  
  31%
  
  I have this stored procedure:
  

  create or replace PROCEDURE sp_Validate2(p_EMP_NO IN VARCHAR2, p_recordset OUT SYS_REFCURSOR)
  AS 
  O_EMPNO EMP.EMP_NO%TYPE;
  
  BEGIN
  SELECT EMPNO INTO O_EMPNO FROM EMP WHERE TRIM(EMP_NO)=p_EMP_NO;
  IF SQL%FOUND THEN 
   begin
     OPEN p_recordset FOR
     SELECT o_EMP_NO AS EMP_NO FROM TAB;
   end; 
  END IF;
  EXCEPTION
  WHEN NO_DATA_FOUND 
  THEN null;
  END;

  Central Unit
  My program getting error when I put exception :(

  There is a problem with a 2 stage approach of:
  1. check if there is data
  2. If there is, return a cursor

  The reason for the problem is that the database and data, can change between steps 1 and 2. What makes the truth in step 1, is no longer the truth in step 2.

  This approach of the 2 step is therefore not reliable or reasonable.

  That is why the traditional approach is for code PL/SQL create ONLY the cursor for the customer and NOT check/validate content slider before sending to the client to use the pointer/cursor handle.

  A cursor cannot be rewound (in this case). So if the PL/SQL retrieves the 1st line to check if there is the release of the data slider, this 1st line extraction went and not seen by the client when it gets the handle of the cursor and it starts looking for the exit of the cursor.

  So PL/SQL uses the parameters supplied by the appellant, apply validation, the logic and rules of business and trades the SQL cursor for the appellant. It then passes the pointer/handle of the cursor to the appellant. The appellant now recovering output cursor. If the output of the cursor is null, no data, then the customer needs to deal with,

  Not only the right technical approach, but also the good functional approach - as the check to see if the cursor output data or no data is a logic gate that the calling client needs to deal with. Not the code that creates the cursor for the appellant program.

• The logic using Soundflower audio recording system

  Let's start with the agreement that I must be a fool.

  I found tutorials on the net for logic audio recording using sound flower and it seems very simple.

  I actually have to make what I want sometimes.

  For the life of me I can't recreate my past successes.

  I'm to the point of madness here.

  I want to just record from Chrome, etc... any audio system, the logic.

  Help, please

  Drew

  1 / set your output to the system on your Mac for soundflower.

  (so now if you play a youtube video or a song on iTunes you won't hear anything - as it is realized in SF).

  2. in line with defined preferences of-> audio-> entry to soundflower

  and something other than control panel the value out of logic (built in output is fine)

  3 / create an audio track and assign to its entrance at Gate 1

  4 / record select the track or you can monitor the track entrance. You should now hear any audio playing on your system (from youtube or iTunes etc) (in fact guarded of logic)

  Press R to save it.

• Create the user account on TARGET Golden Gate

  Can I create an independent account on Golden Gate target.? It's like we do on a logical standby server.
  on behalf of user in question does not exist in the source.
  If so, what are the steps invloved if all this is not normally followed.

  If you want to replicate to create users, create users falls in OTHER DDL (scope). Three scopes are mapped, mapped and other.

  If you want to create a user on the target, there is no restriction on that. The source will never know on this subject (assuming a configuration one-way, two-way, DDL replication is not enabled, or if OTHER is excluded within the scope).

  So, the answer is Yes, you can create any user or users you want to target.