Several timers loop data acquisition

Hi all

I am developing a VI for FPGA Deployment. My equipment consists of a chassis/controller for cRIO-9072 with module 1-9211 thermocouple, card SD-1 module, 3-9215 HAVE modules and universal modules 2-9219. I will collect data of two thermocouples on the 9211, 14 channels on 9215 channels and 6 on 9219 modules. This system communicates to the host via ethernet.

I have prepared a vi (see attachment), which used two DMA FIFO for writing data to data acquisition at a different speed. I will be sampling the s and 9211 9219 much more slow (500ms by samples), than other channels (40 ch/kech. / s). Currently, my FPGA vi trying only to taste two different modules. When I run the present on the host vi and try to read the data, I get only extracts of the data at different intervals. If either of her would reveal latency with the connection or the host vi failed to refresh quite quickly? I am relatively new to labview, so any help is appreciated. Thank you.

Gaussy

Hi Guassy,

There are a few things that you need to change:

(1) you must separate your acquisition in the FPGA in two separate loops if they have to operate at different speeds.  As it is, probably will run at the slower speed of the two parameters.

(2) you must do the same in your VI in real time, or set up the DMA readings so that they will be read at the same pace.  For example, suppose that a single module acquires 1000 hz and the other at 200 hz.  If you want to read 100 samples from the first module (so your reading will occur at 1000 hz / 100 samples = 10 hz), you will need to read 20 samples from the slower module, so it is synchronized with the first module.

(3) your timeouts are too short on your DMA readings.  Your slow acquisition is 500 us.  It will take 50 ms to read 100 samples requested, but the delay is set for 10 ms, so 4 times over 5 playback will return nothing.

(4) you use graphics and no graphics.  A chart will only show the current data buffer that was written for her.  Refresh rate of the façade is nondeterministic, so that you can't see every update.  If you use a chart, the chart will record all data written on it to the indicated depth (default is 1024 elements).

Also remember that you can have three FIFOs DMA between the host and the target FPGA, so use them wisely.  It is often easier to perform your purchases on the FPGA at the same pace and send them through the DMA FIFO even in VI in real-time.  If you need a few channels to connect at a lower rate, you can always throw the excess samples (there are some decimate wave screws that are perfect for this).

I hope that helps!

Tags: NI Software

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