To use the external clock for SCTL myRIO

Hi people,

I'm trying to find a way to get a 2.5 PSM 16-bit ADC, TI ADS1602, to send data to the device myRIO. Ideally, I'd like to bit Records at 40 MHz in order to obtain the benefit of the PSM full 2.5. I know that I can create an 80 MHz SCTL on the FPGA to create a clock of 40 MHz, but when I checked the clock on an oscilloscope signal, it was obviously greatly degraded by bunch speed limits, so he looked more like a sine wave to a square wave. I doubt it would work for use as a clock signal to drive the ADC since ADC specifications say that eligible jitter is around 100ps.

I can use an external oscillator to drive the ADC, but then I have to find a way to sync the clock with clock FPGA 40 MHz. is there any kind of PLL structure that would allow me to sync the clock FPGA myRIO to an external clock? Is there a way to do a loop simple timed cycle driven by an external clock? Or if I was able to customize the FPGA personality to accept a SPI signal up to 40 MHz (ten times her supported limit...), he would be allowed to use an FPGA to ~ 160 MHz and tell him to taste the SPI line each loop and proceed from there?

Thank you!

Hi 3.14159... ,

The myRIO doesn't have the ability to import a clock to use on the FPGA block diagram for clock loops timed cycle unique (SCTLs). The sbRIO-9651 new coming out week OR (not shipping yet) is the only sbRIO who has the ability to import an external clock in LabVIEW. Many of our products FlexRIO also have this ability.

Like you we have it, you can taste the signal at twice the frequency (or maybe more) to and wait an edge trigger to run a certain element of logic. "" "If you open the example Finder and navigate to hardware input and output" R series "FPGA Fundamentals ' triggers and guard dog" trigger detection, this gives a simple example to do this. Once again, since you are eager to taste 10 times the frequency of support, all bets are off, but it may be worth trying.

Tags: NI Products

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