Violation of timing when adding code blocks parallel to each other in a FPGA SCTL

Hey guys!

I have a problem with my code inside a SCTL of running on an FPGA VI and hoped someone could help me.

I work with a 120 MS/s ADC and write the data to the FPGA block of memory in a 120 MHz SCTL. Since the data has to be 'mixed' there is also a code to get the correct address (by first example data at address 0, second to address 20, 40 and so on until 2000, then I start with 1, 21...).

I have a second block of code that later, when writing is completed, reads in the block of memory to perform some calculations (a linear slope of the signal interpolation)

The two parties are implemented using pipelining (I say this because I think it would be the first response of the community), while if I compile only one, everyone needs about 7 to 8 ns to run, which means that they meet the requirements to run in my 120 MHz SCTL (8.33 ns).

But when two blocks of code are in the same field of clock (whether in ore SCTL in two SCTLs using the same clock) from the FPGA VI I get a timing violation, saying that the code in the SCTL needs 17 ns (logical and delay routing) to run. It is not also show me the critcal way, just the SCTL. Because the code runs at the same time, I don't see why the delay of logic should increase (to 12 ns). The only way 2 code blocks communicate with each other are the memory of block and some shift registers so the path of Combinatorics is not increased.

I already checked whether the SubVIs (I use one per block of code to avoid the lack of clarity, but they are different) are the problem. If the code in the SubVIs implemented directly in the FPGA hand VI it does not change the delay of logic.

50% of the registers and the lut FPGA are used, the DSP48s of 5% and 50% of RAM block, so I don't think that the problem is something like the compiler finds not enough free slices to create fast paths.

The main problem is not that the delay of routing increases, but the delay of logic.

Does anyone have an idea what could cause this huge increase by delay time?

I use labview 2011 and 12.4 Xilinx.

Try not to put memory read the node within a box structure. Instead, you can always read from a fixed address, say 0, when the data are not all ready. Reading a memory will not damage your data contrary to push from a FIFO. If your memory by reading the node is inside a case structure, there will be a mux when data is passed outside this business structure, which will increase the delay of logic.

In addition, I also recommend that you do not use the loop of the index 'i', if you are running at high clock frequency. This counter is seen to be 32-bit, and you probably don't have a memory that deeply. LV FPGA is to have logic check inside the read node memory address range, so width incorrect address can still be important. You can implement instead of your counter code which the width of the tip is appropriate.

Tags: NI Software

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