volatility of FPGA data persistence

Similar Questions

• The NI USRP-295xR RIO allows a front-end Ettus BasicRX IF-sampling? And what is the rate of the ADC to FPGA data?

  Hello!

  I'm in the quest to replace some aging PCI-5640R. I am currently using as a portable-Journal data solution, mounted in a Magma Expresscard to PCI box with a laptop. As a reference of the time, I use a Symmetricom XLi.

  The equipment is dependent on the sampling finished a set of samples once a trigger signal goes high and also receive antenna azimuth information using two lines PFI more. The signal is sampled at IF, 30 MHz, and the signal is less than 5 MHz bandwidth.

  Now, I started watching the Ettus X 301 with a GPS OCXO and MXI-express interface which should be the same as the USRP-295xR NI. It is available as device NI RIO with three different front ends, unfortunately, none of them work at 30 MHz.

  Q-1: Ettus has the front-end 'BasicRX', but it is only considered compatible with LabVIEW driver and not necessarily with the RIO. Is the front-end BasicRX usable with the USRP - 295XR RIO and MXI-interface with LabVIEW FPGA? Should I just avoid trying tune the nonexistent LO? As long as he gives me data, I can live with some error messages during the Setup...

  It's the best solution for me, but if it is absolutely impossible, I have a few questions:

  Q-2: information on the front end are really rare in the pages Web OR both Ettus, but the WBX is listed up to 50 MHz frequency, to have a filter of low pass of bandwidth of 40 MHz to I and Q. This should mean a total of 80 MHz of bandwidth with I and combined Q,-40 to 40 MHz. Why did the bandwidth to Web pages as OR listed being "40 MHz bandwidth in real time", if the low pass filter of the WBX is 40 MHz in I and Q? Not the band total bandwidth or 80 MHz?

  Q-3: assuming a bandwidth-40 to 40 MHz: could I put the WBX LO at 50 MHz, be tuned to the frequencies from 30 MHz to 20 MHz signal,-20 MHz and use a bandpass filter to the FPGA to extract the new signals and remove all other signals?

  Q 4: I tried to start a FPGA project in LabVIEW and add the x 301/294xR/295xR as a target. Data clock is locked to 120 MHz, which I guess means he will receive no data to 120MS/s IQ? The x 301 Ettus is listed as provide data of the ADC to the FPGA at a rate of 200 ms/s, could someone explain to me why, OR USRP RIO expects only database 120MS/s?

  Hi Idar,

  Yes, you should be able to put the basics on your X 310/USRP RIO and use LabVIEW FPGA to receive 120 MECH. / s of the DACs.  The example I posted is in fact not for the precompiled file bit.  The example I posted is for LabVIEW FPGA, which allows you to add the IP address for the FPGA.  There is a sample project that comes with LabVIEW FPGA which is the recommended starting point to build your FPGA application.  The sample project has all the configuration set up as well as broadcast continuously and pads/FIFOs in the FPGA and examples for synchronization.  There are comments in the code example that show where he must add your own blocks of property intellectual as a filter and decimater you mentioned.  The PDF I posted shows what changes you must make to this sample project using the Remora Basic/LF.

  I would like to know if I'm not explaining this clearly, or if you have any questions, I'd be happy to help you!

• FPGA VeriStand personality is late? and latent FPGA data processing

  I use a FPGA 7853 (only) in a SMU 1071 chassis with a controller 8135 and run VeriStand 2013 SP1.  At the end of my test, I want to ensure the integrity of the test, which includes the audit of the FPGA interface is never late.

  I first thought to expose the terminal 'Is?' late as a channel, but then I noticed it isn't really an account, it's just a flag.  In addition, it seems that this flag is not locked, it does report by iteration of loop interface.  This makes me think that I alarm an VeriStand on the later is for VeriStand FPGA interface design? channel.  Am I correct, and if not, how NOR have I use East late? terminal?

  As the DMA in the FPGA nodes then never expire, there no sense watching the Timed Out? terminals on the FPGA.  But the effect of a timeout will appear in the East towards the end? Terminal Server.  I'm tempted to change the end is? U64 to a real number in the number of late? the defined indicators synchronize to the host VI.  is there a reason to not do this?

  How VeriStand manages a FPGA end?  If the RT side of the DMA buffer became more complete, data from the FPGA would be more latent, which could lead to the instability of the system.  Hopefully the VeriStand engine should purge the latency of the data, but I don't see anything in the FPGA interface which would facilitate this.

  Thanks for your help,

  Steve K

  Hey Steve,

  If the PCL NIVS reads this flag as true, it incrememnts the County of HP system channel.

  For the question of FIFO depth: The PCL is always expected to read and write a # fixed packages each iteration (as defined by the XML) and FPGA always reads and writes the same number of packets of each loop of comm iteartion and since the timeout is set to-1... orders may not be combined. Packets act as a handshake.

• 5154 digitizer for fpga data

  I am trying to stream as quickly as possible from the to a FlexRIO 7966 5154 digitizer.  From the example "NISCOPE fetch Forever" in LV2012, I can implement the acquisition on 5154 @ 40MS/s, 50 k of data I8 piece and the graphical indicator seems to keep well indefinitely.

  I tried then write data to an FPGA - FIFO target host, and it chokes.  With FIFO write the method inside the loop of 5154 fetch the 5154 ends in error because of the "overwhelming memory" (it fills its on-board memory until the HOST is reading).   With FIFO writing in a parallel consumer (queue conduit) loop, the queue overflows just because he can't write that as fast as the 5154 FIFO provides samples in the queue.   What Miss me?  The 5154 uses a PCI DMA bus (I think), so I think that if he could hold, the host to the FPGA PCIe bus must be capable.

  There is another factor, that I have not taken into account?   Sorry I can't provide the VI since the installation of the LV is on a PC not connected to the network.  Any advice or suggestions would be appreciated.

  Thank you

  Mark Taylor

  For future reference, I ended up resolving this by moving the implementation on the actual FPGA.   I had run in mode "on the development computer with i/o simulated" and no matter what I did with the start-up or sizing FIFO sequence, it just doesn't work.

  After compiling and running on the FPGA, all right.  Maybe it's the basic knowledge, in fact I remember somewhere in my travels reading that don't accurately represent timing problems when running to the old fashion, but LV FPGA has kind of us painted into a corner with the compromise of simulation/compilation.  They do not include Modelsim, which is the only tool that enables co-simulation do functional and verification of the timing set (we Questa, unfortunately) and independent VHDL simulation captures the interaction host with precision (and software processing/timing is impossible to quantify!).  In my situation, the only way to operate at speed is in the FPGA, but then I can't see all of the things that I need to see to debug... ARGH!

  Additional links and resources always will welcome (on debugging of FPGA LV and design in general).  I found a couple of things below, which was somewhat useful:

  "NEITHER powerful LabVIEW FPGA Developer's Guide"

  http://www.NI.com/Tutorial/14600/en/

  I found a link to an "FPGA Debug Reference Library": http://www.ni.com/example/31067/en/, but my installation does not seem to have this available.

  And it looks like 2013 may add functionality to help alleviate some of this via the node of the execution of office referred here to the 'Test and debug LabVIEW FPGA Code'

  http://www.NI.com/Tutorial/51862/en/

• fpga data transfer

  Hello

  How transfer two values, an FxP and a single value of the timer, the fpga for the RT host simultaneously so I don't know what timer value is what FxP value on the host of the RT. With DMA FIFO, it is not possible to select "custom control" data type.

  Thanks in advance,
  Dries

  Hello dries,

  There are 2 interesting conversion function that can be used in LabVIEW and LabVIEW FPGA.

  It would simplify the code even further:

  http://zone.NI.com/reference/en-XX/help/371361H-01/Glang/integer_to_fxp_cast/

  http://zone.NI.com/reference/en-XX/help/371361H-01/Glang/fxp_to_integer_cast/

  This should do the trick.

• How to transfer a single RT for FPGA data

  I start working with the CRio-9012, I want to know how to transfer data from the FPGA RT, I found something about DMA FIFOS, however I notice that it is only possible to transfer pictures, I don't know if I'm doing something wrong. I have another question, is it possible global variable usage in the data transfers between RT and FPGA?

  Filipe

  280584 wrote:
  If I try a fifo DMA allows you to transfer data between FPGA and RT, I choose TYPE: ok DMA HOST-TARGET? or SCOPE TARGET must be selected? In this case, my host is the RT and the target is FPGA ok?

  Yes, you will need to use 'Host to Target' or 'Target to Host' (the FPGA is the target, RT is the host); the one who depends on the direction that where you want to send the data.  Target range is for FIFO that is used only on the FPGA. they are useful for transferring data between the simultaneous loops in FPGA code.

• FPGA ~ data acquisition

  Hello, I'm doing some sort of dummy program.  I put in a sinusoidal signal generator to the place where I hope to possibly an acquisition of data vi.  However, whenever I have it take data it spits out hundreds of text files that do not appear to resemble the sine wave I am simulating.  I'm rather new to all this, so any help will be appreciated.  I've included the vi that I'm working on.  Thank you.

  Hello

  You change the option in the measurement file entry for "the file already exists, add to the file" you now get a file with all the data in it. There are also a few examples in the finder example showing how to write to a text file differently if you don't like the format of the data that you write.

• In the store of runtime data persistence

  Hello

  Does anyone know when a persistent data in the runtime store is erased? When I delete the application?

  Thanks in advance.

  If you remove it manually or restarting the device.

• Question WebService data persistence data control

  Hello

  We use a Web Service data on two pages jspx for application control. The control of data attributes are added on the two pages as data binding.

  Scenario: we submit certain data from page 1 using the web service data and go to page 2. Fill in some data on page 2 and again to apply for the data Web Service and after successful response control back page 1. Same thing repeats again and again for this scenario.

  Now the question is, submit us data of page 1, move to Page2, submit some data of page 2 and return to page 1. If repeat us this process, while presenting data on page 1, the data that we presented earlier on Page2 also get submitted, should not. We want only to present data according to the link on this page. Page1 is unlimited taskflow and Page2 is in the stubborn taskflow.

  We tried setting values as: CacheResults: false on iterator, refresh condition: Ifneeded, UsePersistentStructure to false, the control data. Also tried to reset and turn off data using the API and resetInputState on the links. But nothing works. The only method that works is ClearForRecreate on iterator Page1. But since internal its method, it might not be good to use. Also, after the use of this tells us to receive intermittent error indicating AttributeList$ IRB cannot be cast to a string and exception argument is not an array a few times.

  Please let me know, how I can ensure that the correct data are sent to the data control for the web service.

  With the help of JDev 11.1.1.6.

  Thank you

  Solved by removing the option of data relating to the shares in taskflow control.

  Thank you

• Can Flex 2 cause local data persistence?

  
  
  Guys, I just check the RIA development environments. I am aware that the flash local shared objects as a way to store data on a local computer. Is it available in Flex 2? It is essential for the application I want to write. Any help welcome.
  
  Best
  
  Steve

  It's just a local file, although the location is not good publicity. You could encrypt the data Save in it. I used MD5 with Flex library.

  Tracy

• Data persistence of another class

  Hello world. I have a class with an EditField where a user can enter his name. It can successfully be registered and loaded the class, but I'm trying to load the name on the Welcome screen when the next run of the application.

  ProfileBuilder.java

  Class ProfileBuilder {}

  EditField firstNameEdit. PersistentObject namePersist;

  public static final long KEYS = 0xb724a0bb0280b11aL;

  {ProfileBuilder()}

  ...

  firstNameEdit = new EditField("","");

  ...

  Add (firstNameEdit

  }

  public void save() throws IOException {}

  namePersist.setContents (firstNameEdit.getText ());

  namePersist.commit ();

  }

  }

  --------------------------------------

  Class of the Welcome screen

  Menu.Java

  {Class menu

  Menu() {}

  If (ProfileBuilder.firstNameEdit! = null) { }

  name = (String) ProfileBuilder.namePersist.getContents ();

  I forgot initialize the PersistentObject Duh!

  namePersist = PersistentStore.getPersistentObject (KEY);

• Which data persistence option to use given my current problem?

  Hello

  I would like to present my first goal. I need to replicate an application we built for the IPHONE. The app in the IPHONE using SqlLite as the DB. There are 8 tables in the DB. Each table has an average lines 400 and one of the table has 700 lines. Each table has 12 columns. Describing in detail the reason must support my deduction that I need a database full blown rather than, say, persistent object store. Or can I? That is the question.

  I feel I should use SQL DB UltraLiteJ (and not SqlLite since I want to target OS 4.1). Is this a wise choice? If this isn't the case, then what other DBs I at my disposal?

  Much obliged.

  (a) possible, but not easy.

  Table is Vector, line = element, then you must write the logic of handling loads.  Theoretically achievable and we have, but it's because we started when 4.0 was new...

  (b) 75% more than our App World downloads are 4.6 or later.  All 4.6 + devices can be upgraded to OS 5.0.  If someone wants your app so bad, they will modernize.

  'Port', I mean leave your SQL database such as a SQL database and develop primarily for OS 5.0.  As a last part of this evolution, change to another DB usage. Now you will have a better idea what facilities you really need (and thus the level of base OS that you want to return) and you will also have a better idea of the market.  It will also down 6 months on the line, the OS 5.0 will begin to look at some old hat because of the OS 6.0.

• Convert LabVIEW FPGA I16 voltage raw audio data

  I use myRIO 1900 and LabVIEW 2015. On the side of myRIO fpga, the Audio IN Terminal gives values of integer (I16) data, while side myRIO RT the real value will come directly.
  Of myRIO 1900 user's guide (see pages 7 and 8), the value of the full scale of myRIO Audio IN is of +/-2, 5V. In view of this, my value 32767 should I16 corresponds to + 2, 5V and so on... [ Please refer to this ]
  But it's my side RT are does not correspond with the data of the side FPGA data after you have used the above conversion [namely (I16 value * 2.5) / 32767]. I have a dimension value correction factor about 16 i.e. RT = value FPGA converted * 16.
  I can't understand this, please explain if someone has expertise in this.

  Hey,.

  for the conversion, please refer to page 10 of the manual named.

  The form of the value the ADC has a range of 0 to 4096.

  LSB = 5V / 2 ^ 12 = 1.22 mV

  Value of RT = value I16 FPGA * LSB

• Good way to stop and run again a FPGA reference

  Hi guys!

  I have some problems when I try to stop, and then rerun an FPGA vi, I explain.

  I have two DMA FIFO to send data to the FPGA of the CPU and the CPU for the FPGA. When it receives data, the FPGA treats them and sends them to the CPU, and according to the result of the CPU does something. For example, it can be turn on LEDs or to rotate a motor continuous.

  But to do these actions, I have to use a "personality FPGA", i/o pins and LEDs appear to be managed by the FPGA core. So I have to close my reference vi FPGA in charge to receive data from the CPU, make my power on LED and then after raise again my FPGA VI once again, if I don't do LED blink or stay without effect rotation motor... But close and start again the FPGA VI creates problems when running, especially for the previous reading on the FIFO DMA awaiting... I tried to intercept errors on the FIFO to restart the FPGA VI with a good time but nothing... I am lost and I think Miss me something, concept, or something else.

  I can't share my code because I work for a company, but I would like to know if you have VI with this type of structure: a FPGA reference that must be stopped to allow interaction of material with the FPGA default personality then run again, all with good timing...

  I hope I'm clear, but if it is not the case, I can rephrase if necessary.

  Thank you very much for the help!

  Afghow.

  I do not understand why you need to change the bit file is loaded in the FPGA.  Why you cannot add code that handles the inputs/outputs to your FPGA processing?  Why do you still need to send data to the host (CPU)?  Just having the process FPGA data and change the output directly.

• Best way to synchronize several FPGAs

  I have several PXI-7833R FPGA and I need all the AIs to be sampled at the same time (through all FPGA). As I taste all the individual channels to HAVE, I have data (write to the DMA) buffer, scan it and are looking for a trigger defined by the user in a different loop. Once I discovered this in a single channel, I save all FPGA data. Regarding the timing of sampling, I had started, to an FPGA, to send a signal on the PXI trigger line to tell others to try, but I guess that it does not sync. If I founded the ensemble of distinct FPGAS screw off the clock, PXI, how synchronize loops to the sample to the same clock time?

  Thank you

  Hello

  There is a very good example comes with FPGA LV named 'Master-slave of RIO - R Series.lvproj'. Just use the Finder for example to open it.

  It shows how to use the lines of PXI trigger for synchronization of the different measures on multiple FPGAs.

  Hope this helps,

  Christian