decimation in fpga

I am trying to perform a decimation operation into the fpga by capturing a LPF exits

at a slower pace than the filter.  My filter running at 80 MHz and I am trying to capture the

data filter to 40 MHz (downsampling by 2) to complete the extermination operation.

The filter is in a single cycle timed loop and I'm looking data that comes from that

filter using probes that are in the loop slower (running at 40 MHz).  What I see is that the

slower loop does not appear to be updated at the rate of duty.  I expected to see all other

sample of the loop of 80 MHz enter the loop of 40 MHz.  Instead, I see a value which seems to be

held for several cycles.

I use a local variable to pass the data between the 2 loops.  The data appear to be

scaling.  For example, leaving the 80 MHz loop I see a value-13.9375 on the local variable;

I read this same variable in the loop of 40 MHz, it seems to be - 13.312.

I have attached the vi where it is useful.

Kind regards

Chuck

I did have the chance to look at your code, but a few things come to mind which can help.  I think that you run the code in emulation (running on the development computer) mode to debug.  This is a useful feature to find logical errors, but there is no guarantee of timing in this mode.  Therefore, we can assume that the 80 MHz loop runs 2 iterations for each 1 iteration of the loop of 40 MHz.  Which could explain what you see.  I assume that you are running in emulation mode, because you have a constant-1 as a starter on the FIFO nodes.  This is not a valid parameter when you use the FIFO inside a loop timed cycle unique (SCTL).  You need to wire a constant 0 FIFO timeout inside.  The reason is that the SCTL running each iteration within the clock cycle in the material.  There cannot be any code that blocks within the SCTL.  I know a code from your code generation error if you actually tried to compile.  I know that this isn't very useful information in your question, but thought you should know.  Another tip is that there is a functionon rational resampling the FPGA palette.  You can find it under programming > FPGA math and analysis > rational Resampler.  It can be configured for an entire decimation by setting L 1 and M 2.  He'll probably use more resources than your current implementation, but be quite simple.

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