DMA with FIFO data acquisition

Hi all

I would like to ask you a favor to get some help to understand FIFO.  I have attached the files here and simply the target more basic FIFO of host data transfer.  I put the required number of elements to 4095, I understand the depth of the FIFO on FPGA.  The sampling rate in FPGA is 10 kHz.  The loop on read host rate is 10 ms.  The depth in the host FIFO.configure is 10000, which I think is the number of items in the part of host of the FIFO DMA memory.  So I guess that the total thickness of the FIFO is 14095 elements.  I put the points of reading in each iteration to 2000 points.  However no matter how to change the combination and number of points to read, the program performs an iteration and then displays a different error message.

Can someone please help me understand how to calculate each parameter and to optimize it, if the sampling frequency I want on FPGA is data of 10 kHz I16?  Thank you very much.  I appreciate your help!

Best,

Charles

I have attached all the files here, which is very similar to the example on ni.com

Charles Hey,

Regarding the second question, it's what I wanted. I'm not 100% sure how the constraint point converts a dbl in unsigned int, so it would be good to use a node of conversion and to probe this value, to ensure that you get the value you expect.

As for the second question, I told you that you should wiring in a contstant-1 in the field timeout of your fifo method on the RT VI and VI FPGA read.

Thank you

Tags: NI Software

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