FIFO extended target

Similar Questions

• Disable the extended FIFO FPGA target during execution

  Hello

  I use a FIFO extended target in my FPGA to constantly calculate the derivative of a measured value (dB/dt). Thus the FIFO stores all values during time dt. This means dt determines the number of items in the FIFO and dB is determined by the actual value less the oldest value in the FIFO. It works well when I initialize with the code in figure InitFIFO.

  But the FIFO of compensation is not possible (see figure clearFIFO). In the while loop if "reset dB" is false, as the new value of B is written on the FIFO, then the oldest value is read from, for the number of items in the FIFO remain constant. To change dt during execution, I need to clear the FIFO and initialize it with a new length (number of items). I tried the next loop, but it does not work. The FIFO does not initilized with the elements. The length is zero and the loop counter for (#deltaB Length2) is 0.

  What I am doing wrong? Is there a better way to erase a FIFO during execution in the FPGA? I'm now stuck for 2 days with this problem and looking forward to any idea or suggestion.

  Thank you very much. Best regards

  Andy

  Hej,

  Thank you for your response. You were correct, that deltab FIFO length was 0 because the defalt value was zero. The problem is that in my host vi on the RT system I put DeltaB FIFO length in a loop of high priority and as you can see when I restart the FPGA, DeltaB FIFO length has a valid value (the code in figure 1 works well with a local variable of DeltaB FIFO length in the FPGA). But the variable to set the variable "reset dB" is under the control of the loop of low priority of the host vi. And there, I had an entry DeltaB FIFO length unwired.

  So, I learned that a control FPGA read/write unwired sends a '0' or resets the variable to its default value in the FPGA. I assumed that nothing is transferred and the last variable is retained if you let a control read/write unwired. Now, I learned of this stupid error!

  Thanks a lot again!

  Andy

• Reach target FIFO in the event structure will not achieve

  Hello

  I'm just counting the time in ticks between edges mounted on two digital channels. Therefore, I use a myRIO and LabVIEW 2013 SP1 on a Windows 7 PC.

  As you can see in the attached photo, I use a FIFO extended target to switch the number of ticks between two SCTLs events to a while loop, where I want to send them via DMA to host of the RT.

  I chose this model to limit the number of DMA channel and increase the SCTLs clock (allows greater accuracy in time). The number of ticks is determined using the DSP 32 bit - built-in counter.

  However, when I run the VI no data is written to the target FIFOs scope. 'Number of elements to write' is still 127 (128 requestet), 'Number of items to read' is always zero. "ch0 post" indicates that the "real" State of the structure of the case is actually entered.

  Edit: all indicators have been added for debugging purposes. Simulation on PC indicates no error either, but I realized that no data is written to the host of RT during actual use.

  I checked the cRIO programmers guide and the high Performace FPGA Developer's Guide and do not see where I was wrong. However, it will not work.

  I would be happy if someone could help me solve this problem!

  In the lower part while loop what do you do if one of the read FIFO has expired (zero cases in the structure of the case)?

  If you set the Boolean value False in any other case (1.3) then you'll only send something to the host when the two data FIFOs received in the same loop iteration.

  If she receives a number of cycles on a FIFO in an iteration, and a number of cycles on the other FIFO in the next iteration has expired will never be null.

  To debug you may store the value 'tick count ch0 fifo' in a shift register and update only when the delta_c_ch0 FIFO does not time-out. Then you can see if this value is always nonzero.

• Reach target FIFO / missing error methods

  In my project, there are two FPGA vi and 4 pairs (reading and writing) of FIFO extended target that are used to pass data between the two vi.

  A vi FPGA (named rs232.vi) writes the data it obtains from a port RS232 to READ FIFO; also, it reads data ENTRY FIFO and transmits to the ports.

  The second vi FPGA (named griffin commands.vi) writes data to WRITE FIFOs and reads data from READ FIFOs. There is no other vi in the project.

  When I try to run either of the vi, I get an error about missing methods to FIFOs. For example, when I run rs232.vi, I get an error requiring a reading memory FIFO so that the read method (see the image named side rs232) and who should write FIFOs have Scripture metod presend on the vi block diagram. However, these 'missing' methods are present in the second FPGA (as I described above). The same type of error appears when I run the second.vi.

  Why the compiler can't see I have all the methods; However, they are in 2 separate vi? How can I avoid this error?

  SophieJS wrote:

  Why is - a VI is not the top level vi?

  It would be nice too, as long as one of them call each other. I don't see in your screenshot, however.

• Only the 32 block RAMS and always showing error 3 used

  Hello

  I work on Photons counting upon arrival at DIO0. Short cut, there is a lot of data to come and I need to send it to the host as soon as possible. To do this, I used a FIFO extended target in a loop timed under unique bike and another target host FIFO taking this extended FIFO target data and send it to the host.

  According to the analysis that I did, I need FIFO to 600 000 elements Boolean deep target. This should be possible since I use an FPGA virtex-5 wx30 FPGA which has 32 (36kbits) block of RAM. However, when I increase the number of items in this requested FIFO, compiling just can't say that code does not fit into the FPGA while it shows that only 3 of the 32 RAM block have been used.

  I tried to search a lot on any restrictions on the FIFO, but I have not found.

  Please help me here earlier.

  I have attached the file VI and the sheet of newspaper of Xilinx compilation.

  There are 6 FIFOs in this project:

  The target host DMA (items I32, 1023)

  Target to host DMA (Boolean elements, 2000)

  Target to host DMA U32 (U32, 500)

  Range of target DMA write (I32, 16000)
  County of DMA scope target (Boolean elements, 108000)
  DMA County U32 brought target (U32, 500)

  There is a bug in the compiler to Xilinx that not all types of block instantiated Rams are reported.

  I did a similar discovery before.  http://forums.NI.com/T5/LabVIEW/FPGA-block-RAM-FIFO-resource-usage/m-p/2978897/highlight/true#M85572...

  Therefore, simply ignore the statistics of the compilation, they are wrong.

  Block of RAM is not addressable as 36 k x 1 bit, it has 36 bit width or width 72 bits.  This means that 1-bit, 2 bits, all the way to the top 36-bit all fill a cell block of RAM.

  Therefore, your consumption will be 600 k x 36 bit which gives much more than what you're supposed to be bit 1 x 60000 storage trequirement.

  1x600k is part of the block of 32x36k RAM (600 KB required, 1 MB free space)

  but the reality is that

  36x600k does not fit in the block of 32x36k Ram (21 MB required, 1 MB of free space).

  If you can, try little racing Booleans in one FXP 36 bits before writing in the block of RAM will improve you things.

• Rinse the target DMA to host FIFO FPGA

  I have a program that runs on FPGA waiting for a ppr pulse 1 a coder, then begins to acquire data based on 4096 pulses of ppr. After that it becomes 4096 pulses, it synchronizes the back upward with the pulse of 1 ppr and recidivism. If the encoder stops spinning in the middle of a revolution, I have a timeout will happen, shouldn't get a pulse of 4096 in some time. This way my code isn't stuck wait pulses if the encoder stops turning. Then, it warns the user and synchronizes backup with the pulse of 1 ppr when spinning resumes.

  Well, the encoder stops at Midway through a revolution of spinning, I get a timeout, but now there are 2048 (4096 ppr * 0.5 revolutions) stale data points in the FIFO. I want to get rid of these points so that once it syncs back upward with the pulse of 1 ppr, I have data in the FIFO, all of the current revolution. I guess I could take the timeout error and trigger a loop on the side of RT that removes the elements until the FIFO is empty, but if it is not in time, before the encoder starts to turn once again, I still stuck with stale data. Maybe I need some sort of handshake with controls? I could also put FIFO for target on the FPGA for storing data and not the tail it to go to the host until it is all there. If I get a timeout, I could please rinse on the FPGA FIFO, because there is a method for flushing to target FIFOs.

  No matter which deals with this problem before, and how to solve?

  Hello

  I think that your first method is the best option. When you save a timeout, have triggered a case on your side of RT first making a FIFO reading which returns the number of items in the FIFO (but reads the items suck) and then immediately do a read FIFO that reads the number of items remaining. This will clear your FIFO and it should run quickly.

• Change FIFO size externally

  Hi all

  I'm using LabVIEW 2015 with FPGA module.

  Can you change the size of large FIFO external target (using a control, for ex, attached to the FIFO) without having to access the settings menu?

  Thanks in advance.

  Here's the thing with FPGA: nothing can be dynamic.  So, no, the FIFO can be programmed from anywhere but the settings menu.

• variables of user-defined data transfer

  Hello

  I use the etherCAT 9144 chassis and is only supported by this hardware FIFO range target. After a search, I realized that the only way to transfer data from FPGA to the host by using user-defined variables. But these variables do not support the notion of FIFO. So which is the best practice to transfer data after measures (provable 10 Hz measurement of 15 values) to host VI?

  Thank you

  As mentioned, the 9144 only supports the analytical engine.

  In regards to what you do, it really depends on the entire application. For example, what is the master? Are there other systems at issue here? Etc. It's a good read, in general, although it might not help this second right: http://www.ni.com/white-paper/14151/en/

  A high level, you need to decide what you need. If you have need for deterministic communication, low-latency over long distances from a RT controller, the 9144 is probably the right choice. If you need low latency + streaming over short distances to a RT controller, you should look into the RIO MXI chassis. If you need mainly not deterministic low speed (10 hz) data mixed with low flow continuous over long distances to a windows or host RT, then ethernet expansion rio (9146,7,8,9) is probably the right choice. If you need high speed continuous with low control latency over long distances to a windows or RT host, you need a full cRIO controller. Based on what you've posted so far, its uncertain is the right person.

  Lets say you're stuck with the 9144 for now. As you can easily hit 1 kHz scanning cycles, it should be perfectly possible to data 'stream' to 10 Hz. If you run the scan at 1 kHz engine, then you are 100 x oversampling. Where it gets complicated is this requirement of sync. By default, acquisition input/output is synchronized to the clock of the scan (and you can see when the clock of scan is set by a knot of e/s FPGA). However, you can take complete control of a module in the FPGA and read inputs and outputs at any time if you please. In other words, you can set up so when DIO0 goes high you immediately enjoy all the values of AI 15. You can then transfer these values HAVE switched to the host using the user-defined variables.

• Target to host DMA FIFO - actual number of items

  Hello

  I have a target of FIFO of DMA host using memory block. Under FIFO properties, "the actual number of elements" is indicated as part of 1023.

  But when I wire a remaining indicator to the 'elements' of FIFO in the host of VI, said 16384 elements. And I read a lot of part of the FIFO.

  Why is the actual number of items that much more?

  The data type is 32. And I have a high-7965R FPGA.

  See you soon.

  There are two different buffers for the FIFO: one on the host, the other on the FPGA.  Data is copied from one to the other.  It may be more space allocated on the host, because there are more memory available here and the loop of the host, probably runs more slowly than the FPGA.  You can set the host using a node to invoke FPGA FIFO set the buffer size value.

• DMA FIFO (target host)

  Hello

  I have the next vi FPGA and RT vi (joint). I'm trying to transfer data from the FPGA to the RT vi (using the target to host DMA FIFO), then to plot the data in the RT vi. The signal that I take analog input also is a 10 Hz, 1 well module 9215 V sinusoidal amplitude.

  However, in the RT vi, I get only one exit fluctuating, with only the values 0 or 1. Also I see no time-out that happens with the RT parameters vi as: 'TimeOut = - 1' and "Count (uC) = 25".

  Why would this be happaning?

  Thanks in advance...

  Mandar-

  Hi Mandar,

  Not with 8.6. You told me 8.5 documentation (I didn't know you were using this version). Take a look at the following article; It should solve the problem that you are facing:

  How can I transfer my data to fixed-point using a FIFO in LabVIEW?

• How is managed using DMA FIFO (target host) host matrix

  Hi people,

  I'm trying to pass an array of values of the host to the FPGA using DMA FIFO. Let's say 20000 items in the table. My FIFO host side can contain only 16000 items or almost. The data will be written element by element regardless of the size of the table or do I need to partition the table in small paintings before writing the FIFO method? Let's say that I write for the FIFO with berries small, 1000-element. The FIFO will read 1 element both of the side FPGA so the stream is blocked until I have at least 1000 free items on the FIFO method write, how he writes every 1000 the next setpoint at the same time? Or target values will be written permanently as soon as the individual elements are erased by the number of available items to write?

  Hi Nathan,

  Sorry for the late update, but I just thought that I should follow. I followed your advice and try it tested just for me (I probably should I have done it before posting). Turns out that the data table will write even if there is not enough empty elements to contain the table in its entirety. However, it always crashes until enough information is read and erased from memory on the side FPGA for the whole table. So if it's data that are constantly being played, it's always better transmitting data through in the form of smaller tables if you do not want to increase the amount of memory FIFO host OCCUPIES on your system. However, if you can afford the memory while you mentioned, you can always increase the depth of the FIFO on the host side. As I understand it, try to write more big berries to a host to target FIFO buffer does not diminish overhead costs (as is the case with a target to host FIFO) as it still passes an element at a time to the FIFO of FPGA-side without worrying.

  Thanks again for your help.

  Kind regards

  John has

• FPGA target host DMA FIFO multi-channel

  Hi people,

  I have a little trouble to collect my FPGA application data. The control of my FPGA application loop is running and read data from set point between a host and target FIFO to a period of 50 uSec. I run a separate loop to write data collected form two channels in a target of FIFO host over a period of 1000 uSec. I'm taking the data from both channels and its reading on the host in bundles of 500 data samples. The first problem I have is that my method of reading times unless I put my data acquisition loop to run at a much slower pace. My FIFO depth host side is 60000, almost as large as the total number of data samples that I expect to collect in total.

  I have another problem when trying to write the data to a table. Even if my method of reading does not expire, I don't think that will record the first beam of data that are read. I've initialized an empty table outside my acquistion of the side loop host and used the table VI build to take the current data set and add it at the end of this table. I then store in a shift register and pass it in the next iteration where I try to join the new data set to the old and so on. I expected to get a table with all the data, but as I said I'm only collecting the first set of 500. I wonder if my program structure is correct. Any help anyone could offer would be greatly appreciated. I have attached a few pictures of my reference request. Thank you.

  Hi Daniel,.

  Thank you for your response. I think I found a solution to the problems that I had. Looks like it was a combination of a couple things. First, the data acquisition loop was running not until the movement was already over since I plugged the condition to stop the loop of writing deposit directly on the data read loop. This problem has been fixed by creating a shared variable for the stop condition and it wiring to two loops independently. This explains why I got only the first set of data, as it was stored in the FIFO until the end of the movement. However, the FIFO of feedback was still time. Before attaching the stop condition error, I placed a probe on the "items remaining" wire of the read method and concluded that there was only 1023 elements (the depth of the FIFO on the side FPGA) even if I set the FIFO depth host side to 60000. "» I realized it was originally due to the Read method not called for the first time until the end of the movement. Although the problem of break for most fixed condition this problem given that the Read method was now called during the movement, I decided to take a preventive measure and calling the 'Start' before the movement FIFO method is started just to make sure that the memory of PEP on the side host is available immediately.

  So yes, it turns badly I put sync settings have been well after all. Good call on the reversal of the order on the Array function to build. Oh, and I also had to move the waveform diagram to until the table is built so that it is not Replot the old data on top of all the new data it receives. On the same note, I moved to the indicator in table at the end outside of the loop of reading. Thanks again for your help.

  Kind regards

  John has

• Demultiplexing FIFO on FPGA target

  Hello

  Is there a 'best practices' for the multi-channel DEMULTIPLEXING from one host to target FIFO in an FPGA? All of the examples I can find only discuss multiplexing on the FPGA to pass multiple channels of data to the PC, (the scenario of "reverse") who seems simpler.

  On a related note, is it possible to play more than one sample of a FIFO by clock using parallel FIFO read nodes?

  Thank you

  "what interlacing out side of FPGA should look like a chart, and if there is a favorite answer"manual"

  Have a separate loop off interlaces the data and transmitting values to individual single channel FIFO is a very common model, enough so that I would say you usually want to start with this approach if each channel can be treated individually (i.e. in parallel with separate loops).

  If the strings must be addressed together, then it is more common to have a loop that creates a single table for each set of samples of channel and then passes this array by a simple FIFO to the processing loop.

  In both cases, the control FIFO logic must maintain the flow correctly as long as you use indicators of exceeding time limit or the handshake correctly.

• Large number of samples by FIFO - avoid the saturation of the buffer target

  My hardware is a PXI system, with a 7952R module FlexRio FPGA and a 14 bit 250 digitizer MECH NI5761. / s.

  Most of the posts I've seen facing some Mech acquisition rates. / s or less and the number of samples of a few 1000. In addition, my analog read as well as write FIFO is in a SCTL don't while loop.

  I want to buy say a 100000 samples each folder at the rate of 250 Mech. / s or more (millions of samples) at this rate.

  Here's the basic problem I condensed (I think that is). I use the example of the Acquisition of SingleSample as a test project.

  The FIFO DMA includes if the target and the host buffer. In practice, the maximum number of items that the target buffer can have is 32767.

  Now, once on the host, I request more samples to 32767, the memory stream buffer target above (overflow), the host THAT FIFO read node waits forever, until finally the time-out has been reached and the number of items remaining in the FIFO (I guess the host buffer) get enormously large (scales with the time, the read node waits (plus I Specifies the time-out is the largest the number gets).

  This is even if the depth of the FIFO is quite large (the host buffer is 5 x the number of samples per record).

  First of all, this suggests that the DMO transfer rate is too slow. However, this also happens if I acquire only 125 MECH. / s (take 2 samples of ns, which means 14 bits 8 x 125 Ms, so about 250 MB/s. This is well below the rate of transfer, as far as I know, so it should not be the reason. Or am I oversee something?

  The only solution I see is to limit the size of the records up. 32767 elements at a time.

  Someone at - it experience with large quantities of samples on a FPGA - digitizer using a FIFO for reading configuration?

  Just run the example CLIP unique sample vi and try to acquire 1000 samples, it will work. Try to acquire say 10000 samples and it will timeout as described above.

  Thank you!

  
  

• Target to host DMA FIFO not compensation when they are arrested

  I use a PXI-7841R (Virtex5) and 32-bit data to the host via DMA FIFO transfer. When you read the FIFO on the host for the first time, the data are "stale" (which means that it is not what is currently coming in the FPGA, but what came in a few seconds ago stale). I tried both a stop and a configuration for clear memory FIFO before I use them. Documentation on one or both of these so-called clears the target and host the FIFOs. Does not help in both cases. With readings of the second and the following, FIFO has then 'valid' (same data as it appears on the FPGA entry node). What is curious is that each reading exactly the same thing:

  1. Stop the FIFO (must erase all data)
  2. Elements of reading 375 of the FIFO. (repeated playback of the FIFO)

  Also interesting: FPGA FIFO is implemented for 255 elements. The first 255 items host-side contain the data "stale" on the first reading. It reminds me of the never erased FPGA FIFO.

  Answered by support OR. The documentation for the FIFO, stop and configure FIFO is in error. Cars of documentation will be written against them.

  Solution:

  These methods remove only the FIFO on the side host. Data FPGA FIFO must be read following until no element.