FPGA and arbitration records

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• How to acquire with NiScope at different sampling frequencies and lengths Records?

  I need to acquire the data of 2 channels of the NI PXI-5114 map two different sampling frequencies high, at the same time. Also, I put 2 different record length. Is this possible?

  I understand that 'Vertical' settings can be configured for individual chains because the function 'Vertical niScope Configure' has 'channels of entry with which we can assign the desired channel. But for horizontal settings such as "min sampling rate" and the record min length, I could not find such an option to specify the channel. Would it not common to both channels?

  I hope that the device is capable of simultaneous sampling and therefore channels can be configured individually to different sampling rate.

  Hi AJ_CS,

  Why do you have to be distinct from sampling frequencies on channels separated from the digitizer even?  What different sampling rate do you want?

  But for horizontal settings such as "min sampling rate" and the record min length, I could not find such an option to specify the channel. Would it not common to both channels?

  You do not have an option to configure the settings of hoirizontal on a channel by channel basis because this concept does not exist in the traditional sense of the use of a scope.  Compatible with the concept of IVI, an oscilloscope traditional benchtop will have only a button or a set of buttons for setting the parameters of synchronization of the unit.  There is therefore no horizontal configuration to separate channels on the scanners NOR.

  I hope that the device is capable of simultaneous sampling and therefore channels can be configured individually to different sampling rate.

  Similar to a traditional benchtop oscilloscpe, the device is capable of simultaneous sampling.  But as mentioned above, the channels can not be configured for different sampling frequencies high.

  However, you can ignore data that you think is not relevant.  For example, if you assign 100MS/s CH0 and CH1 to 50 MS/s, then you throw all other samples.

  Alternatively, you can use separate scanners (a channel on each digitizer) and configure them to taste at different rates.  You can set frequencies of sampling on scanners NOR separated and even synchronize them with TClk.

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• FPGA and digital i/o Modules

  Hi all

  We have NI 9421 digital input and digital output NI 9472 Modules. We can run these modules into a VI under the 9073 cRIO chassis. While we have added the FPGA target under the same chassis, we cannot use the modules. We also install the scan engine.

  How can we use FPGAS and i/o Modules at the same time?

  Once you add a target FPGA in CompactRIO chassis, when you deploy the code, the cRIO is configured for the FPGA mode, which requires a bitfile compiled to connect with the C Series modules.  Remove the target FPGA or changing the mode of chassis in the project and by redeploying must reconfigure the cRIO for scan Mode, which allows you to use the IO module directly from the RT VI.

  For more information, see this post.

• What is the use of FPGAS and how it differs from the IO Modules

  Hi all

  Maybe it's a silly question for most of you.  But I have very less knowledge about the basic concepts of electronic (FPGA, real-time) to cRIOs. I know that FPGA

  can be used to generate circuits within the chip that helps by some logical functions.

  I've just started working in the cRIO.  My question is that we have Modules e/s making it outputs all the application entry.  So, what is the purpose of e/s in the FPGA.

  Lets consider that we entered for an application of RTD.  In this case the module NI 9217 itself exits 24 bits of data from the RTD measurement which may be the process of the LabVIEW VI.  What will be this FPGA between the i/o Modules and the processor will help in?  Also I want to know what type of communication is used to send data between the FPGA and host modules.

  Thanks in advance

  Ajay HI:

  Sorry, you do not have an answer to your original question. However, you are right about the benefits of the FPGA. You said, if you build pre-processing in the FPGA, you can unload a lot of potentially CPU calculations out of the host processor. In addition, the program running on the FPGA is highly deterministic and can run the code very quickly. So if you build a kind of guard or evanescent dog part of your application, the FPGA is a good place to put it.

  To answer your other questions, communication between the modules and the FPGA is generally above the SPI and the data can be transferred between the FPGA and host via DMA FIFO operating on the PCI bus or single point save access using read/write in the FPGA host Interface controls. You can also use interruptions in signal of disputes between the FPGA host.

  I hope this helps, but let us know if you have any other questions.

• Number of DMA FIFO of items to read mismatch in the FPGA and RT

  Hi all

  I use myRIO, LV14 to run my application.

  Request: I have to continuously acquire data via FPGA and host RT process once every 2000 samples are taken. I use DMA FIFO (size 8191) to acquire data, use timeout property in the FPGA to eliminate the buffer overflow. I had followed cRIOdevguide to implement this part. An excerpt of what I put in place is attached. All code runs in the SCTL at 50 MHz.

  Question: Two or three times I met with this strange behavior, the FPGA FIFO gives continous timeout and the RT is unable to read the FIFO. The number of elements to set the property in the FPGA VI gives 0 showing that FIFO is full and no more can be written, but the RT, remaining items gives 0, so it is reading 0 (none) elements.

  Solution: I put a case where I'll write to FIFO (under the code) and if the number of elements to write is different from zero. It seems to work fine, from now.

  What confuses me, is that my FPGA VI said that FIFO is full (number of items to write 0 = FIFO) and gives a timeout error, but RT VI said that number of items remaining in the FIFO is 0 and therefore no data is read. No idea why this is so? My RT and FPGA VIs continues to run, but with no gains or to read data.

  A few minutes after you run the code, I've seen this behavior. No idea why this happens? I try to reproduce the behavior, and will update if I meet with her again. Sorry, I can't post my code here, but I guess the code snippets to explain some extend.

  Thank you

  Arya

  Edit: Even with the mentioned workaround solution, the problem persists, now that the FPGA written any of FIFO. And the RT VI is not able to read all the elements he sees 0 items in the FIFO. The FIFO continues to be in a State of timeout. So I guess that the problem is on the side of RT.

  Why it looks like you read from the FIFO even in two different places in the same VI, at the same time? If the lower reading throws the FIFO, it will never trigger the reset, which could lead to the situation you describe, I think (it's hard to tell from a few screenshots).

  Also, your logic seems too complicated. I immediately noticed that there is no reason to select the entry, the output of = 0 - simply use the 'equal to zero' output directly. On the side of FPGA, why you need check the number of items that you want to write? There's nothing wrong with writing in a FIFO that is already full. just the data won't get written.

• How to use the target FPGA and co. on the same chassis cRIO?

  I have a cRIO system consisting of a master chassis 9074 with several modules IO and EtherCAT 9144 slave unit.

  I want to run a CIE (see: http://zone.ni.com/devzone/cda/epd/p/id/5333) on the chassis of the master, this uses the analytical engine. At the same time I have to do some very urgent measures if I want to use the Board in hybrid mode, using analysis and FPGA engine at the same time (as described here: http://digital.ni.com/public.nsf/allkb/0DB7FEF37C26AF85862575C400531690.)

  But as soon as I add the FPGA target at one of the chassis, the feature of the ice on this chassis stops working. After some research, I found that the CIE can initialize is no longer the modules belonging to the frame that has the target FPGA on it. Error in the method Init of the CIE is: 65700 (indeterminate). This occurs when you try to use "for a more specific class' on the modules configured with a target FPGA on it.

  Someone knows what can cause exactly this problem and perhaps provide a solution/work around?

  Many thanks in advance.

  Hybrid mode requires you to have a bitfile compiled running on the FPGA to be able to read the Scan Interface IO Variables.  Move the target FPGA at the RT target module will allow Interface of scanning for this module, but the frame will always mode Interface of LabVIEW FPGA.

  

  To get fair access to the scan mode for the frame, right click on the chassis in the project, and choose Properties.  Then, modify the Scan Interface programming.  If you want to continue using the programming of FPGA and the Scan Interface set (hybrid mode), you will need to compile a bitfile (empty if you do not want programs on the FPGA again or containing your FPGA code).  By compiling, the support of the module scan mode for the modules under your RT chassis is compiled in your custom bitfile.  Then, on your VI RT, you need to use reference FPGA VI open to your newly compiled VI.  Once this VI is deployed and ongoing implementation, you get the data from you are the CIE.

  For more information, see this knowledge base article and Reference Interface of Scan CompactRIO and procedures.

• LabVIEW FPGA and real-time communication module

  Hi all

  I created a small program in labview FPGA which gets continually distance from the HC - SR04 ultrasonic sensor. The rest of the robot program is written in the time module real Labview. Is it possible that the distance calculated by FPGA module to read in time real module.

  I used the FPGA just because there micro-deuxieme counter, which helps me get the distance from the ultrasonic sensor.

  Thanks in advance.

  There are many ways this can be done, according to your needs.

  See the help article transfer of data between the FPGA and host (Module FPGA) for a breakdown of each method.

• Card FPGA and data acquisition synchronization

  Hi, we are control and data acquisition of several hardware devices (including Photodetectors and translational stages). Until last week, we used all the controls and acquisition using a PCIe-7852R FPGA board. However, we decided to move the acquisition part to a PCIe 6363 DAQ card to improve the sharpness of the tension. During the test, I found that the internal clocks in the FPGA and the DAQ cards are slightly inconsistent (not just a phase delay, but a difference in the period).

  I know because I have generated a square wave (period = 20) using the FPGA and gains using the data acquisition card (at a rate of 200 kHz, that is, 1 taste every 5). I have observed acquired place shifts 5 every 5 seconds approximately. Such a change does not occur if the production and acquisition is done using the same Board. Therefore, the only explanation is that the data acquisition and FPGA cards clock frequencies are different. According to my calculations, the percentage difference between their time clock must be 5/5 s = 0.0001%.

  Therefore, I wonder if there is anyway to synchronize clocks between them. Or, is it possible that I can drive the FPGA clock-based DAQ hardware, or vice versa? Also, please let me know if there is something trivial as I fix.

  Thank you very much.

  Kind regards

  Varun

  Hi Varun,

  my post was only one solution...

  Your data acquisition card may take an entry to control sampling of trigger. In this mode, samples draw on a rising edge of the external clock signal. As long as you stay within the limits of the DAQ (100 MHz for your card) material sampling works perfectly. There are even examples coming with LabVIEW explaining how to program your data acquisition card...

  This mode use you your FPGA as clock source sampling for data acquisition. Both will run on the FPGA clock in sync. When the FPGA is a bit out of 40 MHz, so it won't matter because both devices are triggered on the same clock signal...

• What are the differences between LabVIEW and LabVIEW FPGA and LabVIEW RT

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  LabVIEW RT (LabVIEW Real-time) combines graphical LabVIEW of programming with the power of a real-time operating system, allowing you to create applications in real time.

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  <af:panelGroupLayout id="pgl1" binding="#{viewScope.formBB.mainPGL}">
          <af:iterator id="i1" value="#{viewScope.formBB.allEmployees}"
                       var="emp" rows="0" varStatus="vs"
                       binding="#{viewScope.formBB.iteratorBinding}">
            <af:panelFormLayout id="pfl1" maxColumns="4" rows="1" labelAlignment="top">
              <!--<af:outputText value="#{vs.index}" id="ot1"/>-->
              <af:inputText label="First Name" id="it1" value="#{emp.firstName}"
                            autoSubmit="true" required="true"/>
              <af:inputText label="Last Name" id="inputText1"
                            value="#{emp.lastName}" autoSubmit="true"
                            required="true"/>
              <af:commandImageLink text="Delete" id="cil1"
                                   immediate="true"
                                   actionListener="#{viewScope.formBB.deleteEmployee}">
                <f:attribute name="index" value="#{vs.index}"/>
              </af:commandImageLink>
            </af:panelFormLayout>
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                            actionListener="#{viewScope.formBB.addNewEmployee}"/>
          <af:spacer width="10" height="10" id="s1"/>
  </af:panelGroupLayout>
  

  Delete the Action listener for the bean

  private List <Employee> allEmployees;
  public List getAllEmployees() {
          return allEmployees;
      }
      
  public void deleteEmployee(ActionEvent actionEvent) {
          int index = (Integer) actionEvent.getComponent().getAttributes().get("index");
          if(allEmployees != null && allEmployees.get(index) != null) {
              System.out.println("Emploeye Name:" + allEmployees.get(index).getFirstName());
              allEmployees.remove(index);
          }
          //AdfFacesContext.getCurrentInstance().addPartialTarget(mainPGL);
          AdfFacesContext.getCurrentInstance().addPartialTarget(iteratorBinding);
              
      }
  public void addNewEmployee(ActionEvent actionEvent) {       
          Employee addE = new Employee();
          if(allEmployees != null) {
              allEmployees.add(addE);
          }
          else {
              allEmployees = new ArrayList <Employee>();
              allEmployees.add(addE);
          }
          AdfFacesContext.getCurrentInstance().addPartialTarget(mainPGL);     
      }
  

  Jdev version - Build JDEVADF_11.1.1.7.0_GENERIC_130226.1400.6493

  POC Application - https://drive.google.com/file/d/0BysBrGAsXoo0Qjh3VGkzZkRGck0/view?usp=downalod

  Help, please.

  You probably need to reset submitted values.

  For this, you can use this util class: ResetUtils (reference Java APIs for Oracle ADF Faces)

  For example: ResetUtils.reset (iteratorBinding);

  BTW, you should never bind components to bean managed with a scope greater than the scope of the request.

  Dario

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