FPGA FIFO (reset and stop) release

I have a question regarding the release of FIFO.  In VI, I use for the collection of data through DMA FIFO, before collecting all loop, I use FPGA reset and after the while loop, I use FIFO.stop.  I have attached the picture.  However I think it is the last great of data I have collected and wrote in a text file of a single keystroke, appears in the second run, after I stop vi (by Boolean JUDGMENT in vi) and then restart the vi.  Seems the data remained in a certain part of the FIFO and has not been emptied by RESET or FIFO. STOP the service.  Is there something that I did wrong?  Is there some FPGA or the vi setting I know not?

Thank you very much!

OOPS. I solved the problem.  It has nothing to do with the FIFO.  I need to empty the table at the end of execution so that it cannot be read and written to the file that I use for recording data.  Thank you very much anyway.

Tags: NI Software

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