Loop of force timed to run on a key

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• While loop inside a timed loop

  Hello world!
  I use:
  -LV 7.1 + real-time;
  -compactFieldpoint;

  When I put some time, I noticed a strange behavior, loop inside a timed loop.  Let's fix loop timed with these settings:

  -Clock 1 kHz
  -1 ms period (Yes, I know it's short...)
  -offset 0 ms
  -Stage 0
  -Take the period of absence (ON) and maintain initial Phase (ON);
  -Timeout:-1.

  So, inside the loo, I put a traditional while loop, waiting (for example) an event will occur, and if this event doesn't happen, my cFP-2020 crashes! I mean, it becomes inaccessible for the debugger, and also, if I run a ping at his address, after a few cycles it becomes inaccessible as ping!

  Obviously, that statement of code lock the fieldPoint, because if I remove the inside while loop all work.

  I know that with 1ms duration, timed loop always the finishing of the delay, but I put the scrapping period missed and timeout-1.
    
  It seems to me that sometimes timed loop add overload heavi programs, I all so that the loop according to the tasks, even if my application has be in real-time!

  Tips welcome! Good day!

  Graziano

  Thank you very much for your answer!
  I'll test the entire application and then look for the best practice... but I still think I'll replace it timed with while loops loops...

  Good day!

  Graziano

• How can I force DAC to run always full load for one of the task that executes the stored procedure? And remaining tasks load incremental in the second and sub sequent executions.

  Hello

  How can I force DAC to run always full load for one of the task that executes the stored procedure? And remaining tasks load incremental in the second and sub sequent executions.

  Thank you

  Jay.

  Hi if your task is running an informatica mapping you can set your DAC task to run the full mapping for incremental and full loads, so tab task just point to the mapping.

  Hope that helps.

  Thank you

• I am trying to change my product key and get a 0x800402c9 error when I run the product key Wizard

  Update product key

  I'm trying to change my product key and get a 0x800402c9 error when I run the product key Wizard, so I am unable to enter the product key

  You must acquire the recovery discs right from the manufacturer - if you're lucky, your office don't reinstall it properly and leave you with the recovery partition that would do the same job.

  Read your manual, on the recovery of the system and try the options there.

  If they do not work, you will need to contact it manufacturer and order a set of htem recovery disks.

• Rate the triggered loop of the timed iterations of TTL

  Hi all

  I have a camera control VI that awaits the shutter of the camera TTL information and use it as a source of synchronization for a timed loop. In this timed loop, the camera is read and analyzed. Program should respond as soon as possible a new image and that's why I put the timed loop to "Throw missing items" so that it does not seek to catch up (events im trying to detect is quite rare and last several frames).

  The problem is this: when I put the camera for a certain numebr of frameworks (e.g. 10,000) sometimes due to discarded frames ever loop iteration number the last number of frame expected and do not remove (it remains to 9.998 for example). I noticed I can stop it by deselecting "maintain phase." However, it is clear to me what happens exactly with these settings in a situation of TTL triggered.

  It is true that the loop passes the new data directly but starts the next loop the correct number of iteration (+ 1)? Or something else happening?

  IM grateful for any help!

  Dear j.win,

  If you deselect the option 'Maintain the Original Phase', in fact you never will reject any iteration, whatever the value "Discard missed items." On the contrary, the loop will try to catch up the iterations of the end.

  Use of a source of external synchronization (for example your TTL) instead of a source of internal synchronization does not change. You can use the 'period' entrance (dt) of the loop timed to specify when the loop is supposed to go (the unit is the "ticks" in the case of an external synchronization source). A value of '1' means that test loop to iterate over all the graduations of external synchronization source. If for any reason any iteration lasts longer than that, you'll have an iteration "end". Also with a value of '1', it is not possible to change the "phase", then the parameter "Initial Phase to maintain" will be defined only weather or not ignore you the iteration. If 'Maintain initial Phase' is set to false, the loop will run immediately after an end iteration to run always, but a little of the latter. If the 'Maintain initial Phase' is true, the loop will run immediately after an iteraion end if the option 'remove point missed' is false otherwise the loop will jump the iteration.

  It's more clear now?

  Kind regards

• While the loop within a box Structure runs only once a target FPGA

  I have a card OR cRIO-9012 RIO for the HIL system. I have a target FPGA file when I use a While loop within a while loop I use the box Structure to check a real condition inside I have the function of activation of the ports and selecting the analog and digital ports. But for my code the code runs only once on repeted times that we have in the LabVIEW environment.

  I also need help to optimize the code. I've seen people using While loop timed in the FPGA target I don't use in both cases.

  I've attached my FPGA with the Version of LV2012 file.

  Waiting for your comments.

  Thank you and best regards,

  Ganesha Moorthy

  You have while loops inside the structure to deal with a constant of false cable to the stop condition. These loops will obviously never stop so browse your outside while loop (containing the case structure) can never.

  This has nothing to do with the FPGA target, the same thing will happen in the development environment.

• Convert single while loop with variable Timing literal to the producer consumer

  I have a controller for a biological system that updates every n minutes or every minute 2n, under certain conditions. My app has a synchronization controller calculates if the current iteration is n or 2n and feeds the output of this calculation in a loop of "Timing" VI in my all. If I understand correctly, this is similar to the issuance of an order of sleep() in a language similar to C and should be avoided. I'm refactoring my code and I heard that they are well suited for this kind of things. Here's how it should work:

  1. Loop begins at the time T, T is saved.
  2. Schedule controller runs and calculates if loop will get minutes 2n or n minutes. This controller will take a number of milliseconds to complete, so we are is more to time T.
  3. Now that the update interval (n or 2n, let's call it u) is known, the loop must until T +u fill.
  4. The PDC is executed, but a number of milliseconds to execute.
  5. The rest of the time until the next iteration of loop should produce the CPU for other processes.

  It sounds to me like it's the kind of a real-time system, although as long as we are in the minute of the original deadline, there will be nothing wrong.

  What the producer-consumer loop would look like? Assumed that the synchronization and the main order controller are separate from the VI.

  
  

• FPGA IO node and loop Question of Timing

  I'm having a lot of trouble to compile a very simple FPGA VI for a system for the acquisition of data on my cRIO (9075, using a single module 9205 cRIO, labview 2012 dev suite, xlinx13).

  At the end of compilation, the error occurs if and only if I use a block of i/o node FPGA.  This picture shows my very simple VI which fails to a compilation:

  

  When I compile, I get this error at the end:

  

  And here are the details of the error:

  

  It is also interesting to note that the 'Timing' summary says I need a clock of 80 MHz, when the on-board clock of 40 MHz.

  For comparison, when I remove the FPGA of e/s node and replace it with a constant, the compilation succeeds:

  

  The need of a clock of 80 MHz disappears also, according to the report of timing.

  Is this a problem with how loops work in FPGA?  I've been reading about "single-cycle timed loops" that guarantee a performance per clock cycle.  I don't have that kind of acquisition rate, and I guess the structure of loop, I created is not related to a single cycle because of the block of metronome, that I inserted.  I guess correctly?  Are there structures of loop for FPGA which is not related to a single clock cycle?

  I also wonder if this error is not to do with my code, but is rather an internal error of the software compilation NOR, in particular the 'niFpgaTimingViolation.py' script mentioned in the summary of the detailed errors.  I got labview 2011 and xlinx 12 installed on this computer before, but they uninstalled before the upgrade.  This is my first project in 2012.

  I appreciate the comments of the community NOR.  Let me know if my question needs further clarification.

  -Andrew

  I solved the problem.

  In case that someone looking for it later (error 61499 niFpgaTimingViolationMain.py that constraintdict is not defined).

  I did a complete uninstall and reinstall my entire LV 2012 dev suite.  Then the same VI used to compile failure began to pass compilation.  Apparently, I had a corrupt file somewhere.

• Update loop under Vi of hand / run multiple Instances

  Hey everybody,

  If I want to keep my code as modular as possible so that I can see any sub or VI.

  One of the SUB vi is permanently offices incase another output is detected. I don't want to make this mark on the main level because I don't want a huge loop in my main.vi and you won't worry about sending shift register valuse to my Subvi for him to function.

  Essentially, I have designed this subroutine Vi and am now trying to constantly be driven from a main.vi

  This hand is simply.

  Cluster of entry--> Sub VI

  Void VI retains a loop waiting for a change request action. Unfortuantely when I change the vale in main.vi the avlues in Subvi don't update. I guess that makes sense, in C, for example when you call Returns you need to wait until the end of the function call to update. Yet, as Labview is so strongly focused on taking SUB vi to do almost everything for you, I can't imagine labview is not able to update these values. I looked around and the answer seems to be global variables. I really don't want to use the because my application will become very big, but I'll use them if I need to.

  Unforunately, when I tried to use my global variable thing, it didn't work.

  1. global Var = Cluster

  2. it's in the Subvi both the main VI.

  3. when I run my code the global variable is not up-to-date on both front sides when I change one of them. I'm doing something wrong?

  A few comments.

  • You have not included the global variable
  • If you want to run multiple instances of the Subvi in parallel, it must be reentrant.
  • As the Subvi is interactive, it must be configured to display the front panel when it is called, otherwise there is no way to stop it ever.
  • All your time loops needed little expects. They have no need to turn as fast as the CPU allows, all other processes of hunger.
  • "Go to under control" is extremely complex and crawling with weird stuff like an ant farm.
  • • The shift register must be initialized to avoid surprises (but you probably don't have it all)
    • Your loop runs one time too many.
    • Avoid the stress points, such as the structure of the case.
    • You can replace this whole thing with for example a table of threshold, no need to loop. (see image below).

  

  Good luck!

• too long in the loops of whlile (timed)

  HY

  I am: routinely labview developer course made, advanced no performance (not even as it may seem, I need that).

  Programm: multi all structure of event loop with lines of command for each loop, more a single elemnt queue for each loop running as a variable. network communication trought the queues is possible! Many hardware addons as controller PXI Motion and IO digital communication, RS232 communication with several controllers different als separated loops. The software also works without connected hardware components.

  problem: lines of "continuous loop" rate should be less than 5 ms, but is about 15ms/iteration at the present time.

  hardware: computers 2core, WinXP32bit, LabVIEW9

  goal: improve rates of loop of the "continuous loop.

  What has been tryied and tested:

  OK, I tried many things, partially with success.

  -make Subvi returning some of them are used many times at the same time in each loop (see hierarchy VI)

  -increase in speed Subvi with code improvements, partially with success

  -Analyze with the profiling of the VI

  Question:

  When I was profiling the performance of my VI, I have identified that summarizing the duration of the Subvi "Continuous loop" does NOT match the current loop duration. they are about 20-30 ms, whereas they should be according to the number of tracks and the total corresponding to 3ms. in other words, it is factor of 6 to 10 slower than it should be in my point of view. I don't really have an idea of why this happens. the printscreen and its corresponding information is without another iteration loop (deque just waiting) running.

  I tried to get more details and made a few tests and comparative analysis with my continuous loop. He showed that this additional time (latency? so high?) is not actually produced by the continuous Subvi and also not part of the loop deque. It seems that almost all the time of the loop is displayed once the code for the loop is finished... and before the beginning of the loop, somehow...

  If you have any suggestions or information, why this is the case, or if you even have ideas for improvements or references, please let me know.

  attached is viewed from the corresponding part of the program. I don't want to the public the entire program for everyone. If you have any ideas or need the code for the specific tests, please send an e-mail directly to stefan.hartmann (at) psi.ch.

  best thanks in advance

  HY

  OK, I found the problem. the long time of iteration is produced mainly due to a queue which was to load and write the string array of 100 x 100 several times by iteration. This is the reason why time iteration actually has been measured so high and produced a further delay by iteration, next to the slot-VI-times.

  I solved this problem by maintaining the use of queues in 100 with chain 1 x 100, where I actually just need a queue by iteration and not the 100 x 100. This means at the time of iteration about 2 Ms!

  see you soon

• try opening a thaat file will work as administrator and password. Itstarts to run and then loops back to error repeating run as administrator

  I am trying to open a program that must run as an administrator, but the administrator and the password do not work. It starts, then the shows and the error message indicating the need for authorization and loops back to 'run as administrator'.

  Hello

  You remember recent changes to the computer?

  The program worked very well?

  Follow the methods below to work on the issue

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  Note: After you perform a clean boot, follow these as to configure Windows to use a Normal startup state from the article above.

   

  Method 2: start your computer in safe mode and check if you can run the file or program

  See the link below to start your computer in safe mode

  http://Windows.Microsoft.com/en-us/Windows-Vista/start-your-computer-in-safe-mode

  Check if you can run the file in safe mode.

  Method 3: Run the system restore to the date when the file or the program worked very well.

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  Note: System Restore does not affect personal files, such as e-mail, documents, or photos. You can only restore files that you have deleted if you have made backups of these files. Programs that are installed after that date will be lost.

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• Power Management and function on Satellite A210-1BD running Windows XP keys

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• Satellite A350 run Vista - FN key causes bluescreen

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  Seriously, I hope someone can help me...
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  Thanks in advance!
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  Hello

  Your laptop is equipped with preinstalled Vista SP2 or you have installed SP2 as well?
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  Please post the result.